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drm/amd/display: Update FCLK change latency

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[Descrtipion]
- Driver hardcoded FCLK P-State latency was incorrect
- Use the value provided by PMFW header instead

Reviewed-by: Nevenko Stupar <Nevenko.Stupar@amd.com>
Reviewed-by: Jun Lei <Jun.Lei@amd.com>
Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com>
Signed-off-by: Alvin Lee <Alvin.Lee2@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Alvin Lee
2023-03-13 18:06:34 -04:00
committed by Alex Deucher
parent ac18b610fd
commit 1991481828
1 changed files with 1 additions and 1 deletions
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2
drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
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@@ -131,7 +131,7 @@ struct _vcs_dpi_soc_bounding_box_st dcn3_2_soc = {
.urgent_latency_pixel_data_only_us = 4.0,
.urgent_latency_pixel_mixed_with_vm_data_us = 4.0,
.urgent_latency_vm_data_only_us = 4.0,
.fclk_change_latency_us = 20,
.fclk_change_latency_us = 25,
.usr_retraining_latency_us = 2,
.smn_latency_us = 2,
.mall_allocated_for_dcn_mbytes = 64,