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drm/amd/display: Implement DPIA link configuration

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[Why]
Training settings need to be applied to DPIA link at start of each
training loop. Note: FEC readiness should be configured before link
training while FEC enablement should be configured once training is
complete.

[How]
- Implement DPIA link configuration function.
- Account for dynamically assigned link encoders during link
configuration.

Reviewed-by: Jun Lei <Jun.Lei@amd.com>
Acked-by: Wayne Lin <Wayne.Lin@amd.com>
Acked-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Jimmy Kizito <Jimmy.Kizito@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Jimmy Kizito
2021-04-12 16:03:11 -04:00
committed by Alex Deucher
parent 178fbb6d55
commit 187c236aac
2 changed files with 43 additions and 4 deletions
Download Patch File Download Diff File Expand all files Collapse all files

45
drivers/gpu/drm/amd/display/dc/core/dc_link_dpia.c
View File

@@ -30,6 +30,9 @@
#include "dc_link.h"
#include "dc_link_dp.h"
#define DC_LOGGER \
link->ctx->logger
enum dc_status dpcd_get_tunneling_device_data(struct dc_link *link)
{
/** @todo Read corresponding DPCD region and update link caps. */
@@ -38,17 +41,51 @@ enum dc_status dpcd_get_tunneling_device_data(struct dc_link *link)
/* Configure link as prescribed in link_setting; set LTTPR mode; and
* Initialize link training settings.
* Abort link training if sink unplug detected.
*
* @param link DPIA link being trained.
* @param[in] link_setting Lane count, link rate and downspread control.
* @param[out] lt_settings Link settings and drive settings (voltage swing and pre-emphasis).
*/
static enum link_training_result dpia_configure_link(struct dc_link *link,
const struct dc_link_settings *link_setting,
struct link_training_settings *lt_settings)
{
enum link_training_result result;
enum dc_status status;
bool fec_enable;
/** @todo Fail until implemented. */
result = LINK_TRAINING_ABORT;
DC_LOG_HW_LINK_TRAINING("%s\n DPIA(%d) configuring\n - LTTPR mode(%d)\n",
__func__,
link->link_id.enum_id - ENUM_ID_1,
link->lttpr_mode);
return result;
dp_decide_training_settings(link,
link_setting,
lt_settings);
status = dpcd_configure_channel_coding(link, lt_settings);
if (status != DC_OK && !link->hpd_status)
return LINK_TRAINING_ABORT;
/* Configure lttpr mode */
status = dpcd_configure_lttpr_mode(link, lt_settings);
if (status != DC_OK && !link->hpd_status)
return LINK_TRAINING_ABORT;
/* Set link rate, lane count and spread. */
status = dpcd_set_link_settings(link, lt_settings);
if (status != DC_OK && !link->hpd_status)
return LINK_TRAINING_ABORT;
if (link->preferred_training_settings.fec_enable)
fec_enable = *link->preferred_training_settings.fec_enable;
else
fec_enable = true;
status = dp_set_fec_ready(link, fec_enable);
if (status != DC_OK && !link->hpd_status)
return LINK_TRAINING_ABORT;
return LINK_TRAINING_SUCCESS;
}
/* Execute clock recovery phase of link training for specified hop in display

2
drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dio_link_encoder.c
View File

@@ -428,6 +428,7 @@ void dcn31_link_encoder_enable_dp_output(
if (link) {
dpia_control.dpia_id = link->ddc_hw_inst;
dpia_control.fec_rdy = link->fec_state == dc_link_fec_ready ? 1 : 0;
} else {
DC_LOG_ERROR("%s: Failed to execute DPIA enable DMUB command.\n", __func__);
BREAK_TO_DEBUGGER();
@@ -469,6 +470,7 @@ void dcn31_link_encoder_enable_dp_mst_output(
if (link) {
dpia_control.dpia_id = link->ddc_hw_inst;
dpia_control.fec_rdy = link->fec_state == dc_link_fec_ready ? 1 : 0;
} else {
DC_LOG_ERROR("%s: Failed to execute DPIA enable DMUB command.\n", __func__);
BREAK_TO_DEBUGGER();