mirrors/linux
2
0
Fork 0
mirror of https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git synced 2026-05-10 05:39:42 -04:00
Code Issues Packages Projects Releases Wiki Activity

arm64: dts: rockchip: add attiny_rst_gate to Ringneck

Browse Source 
Ringneck v1.4 can contain (placement option) an on-board ATtiny
microcontroller instead of an STM32. In normal operation, this
is transparent to the software, as both microcontrollers emulate
the same ICs (amc6821 and isl1208).

For flashing the ATtiny, the SWITCH_REG1 regulator of the board's PMIC is
used to enable the ATtiny UPDI debug interface. If the STM32 is placed, or if
we are running on an older Ringneck revision, SWITCH_REG1 is not connected
and has no effect.

Add attiny-updi-gate-regulator so userspace can control it via sysfs
(needs CONFIG_REGULATOR_USERSPACE_CONSUMER):

  echo enabled > /sys/devices/platform/attiny-updi-gate-regulator/state

Signed-off-by: Jakob Unterwurzacher <jakob.unterwurzacher@cherry.de>
Tested-by: Quentin Schulz <quentin.schulz@cherry.de>
Reviewed-by: Quentin Schulz <quentin.schulz@cherry.de>
Link: https://lore.kernel.org/r/20240926132028.21910-1-jakob.unterwurzacher@cherry.de
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
This commit is contained in:
Jakob Unterwurzacher
2024-09-26 15:20:30 +02:00
committed by Heiko Stuebner
parent 157707e000
commit 1871e6f7c5
1 changed files with 11 additions and 0 deletions
Download Patch File Download Diff File Expand all files Collapse all files

11
arch/arm64/boot/dts/rockchip/px30-ringneck.dtsi
View File

@@ -16,6 +16,12 @@ aliases {
rtc1 = &rk809;
};
/* allows userspace to control the gate of the ATtiny UPDI pass FET via sysfs */
attiny-updi-gate-regulator {
compatible = "regulator-output";
vout-supply = <&vg_attiny_updi>;
};
emmc_pwrseq: emmc-pwrseq {
compatible = "mmc-pwrseq-emmc";
pinctrl-0 = <&emmc_reset>;
@@ -282,6 +288,11 @@ regulator-state-mem {
regulator-suspend-microvolt = <1800000>;
};
};
/* supplies the gate of the ATtiny UPDI pass FET */
vg_attiny_updi: SWITCH_REG1 {
regulator-name = "vg_attiny_updi";
};
};
};
};