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ARM: dts: imx6q-lxr: Add board support

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The Comvetia LXR board is based on a i.MX6Q phyFLEX-i.MX6 Quad SoM
from Phytec.

Add a devicetree description for this board.

Signed-off-by: Fabio Estevam <festevam@denx.de>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
This commit is contained in:
Fabio Estevam
2024-09-13 17:09:06 -03:00
committed by Shawn Guo
parent fb0423d11a
commit 178edf1566
2 changed files with 88 additions and 0 deletions
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1
arch/arm/boot/dts/nxp/imx/Makefile
View File

@@ -211,6 +211,7 @@ dtb-$(CONFIG_SOC_IMX6Q) += \
imx6q-kontron-samx6i-ads2.dtb \
imx6q-kp-tpc.dtb \
imx6q-logicpd.dtb \
imx6q-lxr.dtb \
imx6q-marsboard.dtb \
imx6q-mba6a.dtb \
imx6q-mba6b.dtb \

87
arch/arm/boot/dts/nxp/imx/imx6q-lxr.dts Normal file
View File

@@ -0,0 +1,87 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
//
// Copyright 2024 Comvetia AG
/dts-v1/;
#include "imx6q-phytec-pfla02.dtsi"
/ {
model = "COMVETIA QSoIP LXR-2";
compatible = "comvetia,imx6q-lxr", "phytec,imx6q-pfla02", "fsl,imx6q";
chosen {
stdout-path = &uart4;
};
spi {
compatible = "spi-gpio";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_spi_gpio>;
sck-gpios = <&gpio5 8 GPIO_ACTIVE_HIGH>;
mosi-gpios = <&gpio5 7 GPIO_ACTIVE_HIGH>;
num-chipselects = <0>;
#address-cells = <1>;
#size-cells = <0>;
fpga@0 {
compatible = "altr,fpga-passive-serial";
reg = <0>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_fpga>;
nconfig-gpios = <&gpio4 18 GPIO_ACTIVE_LOW>;
nstat-gpios = <&gpio4 19 GPIO_ACTIVE_LOW>;
confd-gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>;
};
};
};
&ecspi3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi3>;
cs-gpios = <&gpio4 24 GPIO_ACTIVE_LOW>;
status = "okay";
flash@0 {
compatible = "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <20000000>;
};
};
&fec {
status = "okay";
};
&i2c3 {
status = "okay";
};
&uart3 {
status = "okay";
};
&uart4 {
status = "okay";
};
&usdhc3 {
no-1-8-v;
status = "okay";
};
&iomuxc {
pinctrl_fpga: fpgagrp {
fsl,pins = <
MX6QDL_PAD_GPIO_6__GPIO1_IO06 0x1b0b0
MX6QDL_PAD_DI0_PIN2__GPIO4_IO18 0x1b0b0
MX6QDL_PAD_DI0_PIN3__GPIO4_IO19 0x1b0b0
>;
};
pinctrl_spi_gpio: spigpiogrp {
fsl,pins = <
MX6QDL_PAD_DISP0_DAT14__GPIO5_IO08 0x1b0b0
MX6QDL_PAD_DISP0_DAT13__GPIO5_IO07 0x1b0b0
>;
};
};