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arm64: dts: exynos: Add cpu cache information to Exynos5433

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Add CPU caches information to its dt nodes so that the same is available
to userspace via sysfs.  This SoC has 48/32 KB I/D cache for each A57
cores with 2MB L2 cache.  And 32/32 KB I/D cache for each A53 cores with
256KB L2 cache.

Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com>
Link: https://lore.kernel.org/r/20210622130551.67446-2-alim.akhtar@samsung.com
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
This commit is contained in:
Alim Akhtar
2021-06-22 18:35:51 +05:30
committed by Krzysztof Kozlowski
parent c4e40c0144
commit 178a5d90dc
1 changed files with 70 additions and 0 deletions
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70
arch/arm64/boot/dts/exynos/exynos5433.dtsi
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@@ -62,6 +62,13 @@ cpu0: cpu@100 {
clock-names = "apolloclk";
operating-points-v2 = <&cluster_a53_opp_table>;
#cooling-cells = <2>;
i-cache-size = <0x8000>;
i-cache-line-size = <64>;
i-cache-sets = <256>;
d-cache-size = <0x8000>;
d-cache-line-size = <64>;
d-cache-sets = <128>;
next-level-cache = <&cluster_a53_l2>;
};
cpu1: cpu@101 {
@@ -72,6 +79,13 @@ cpu1: cpu@101 {
clock-frequency = <1300000000>;
operating-points-v2 = <&cluster_a53_opp_table>;
#cooling-cells = <2>;
i-cache-size = <0x8000>;
i-cache-line-size = <64>;
i-cache-sets = <256>;
d-cache-size = <0x8000>;
d-cache-line-size = <64>;
d-cache-sets = <128>;
next-level-cache = <&cluster_a53_l2>;
};
cpu2: cpu@102 {
@@ -82,6 +96,13 @@ cpu2: cpu@102 {
clock-frequency = <1300000000>;
operating-points-v2 = <&cluster_a53_opp_table>;
#cooling-cells = <2>;
i-cache-size = <0x8000>;
i-cache-line-size = <64>;
i-cache-sets = <256>;
d-cache-size = <0x8000>;
d-cache-line-size = <64>;
d-cache-sets = <128>;
next-level-cache = <&cluster_a53_l2>;
};
cpu3: cpu@103 {
@@ -92,6 +113,13 @@ cpu3: cpu@103 {
clock-frequency = <1300000000>;
operating-points-v2 = <&cluster_a53_opp_table>;
#cooling-cells = <2>;
i-cache-size = <0x8000>;
i-cache-line-size = <64>;
i-cache-sets = <256>;
d-cache-size = <0x8000>;
d-cache-line-size = <64>;
d-cache-sets = <128>;
next-level-cache = <&cluster_a53_l2>;
};
cpu4: cpu@0 {
@@ -104,6 +132,13 @@ cpu4: cpu@0 {
clock-names = "atlasclk";
operating-points-v2 = <&cluster_a57_opp_table>;
#cooling-cells = <2>;
i-cache-size = <0xc000>;
i-cache-line-size = <64>;
i-cache-sets = <256>;
d-cache-size = <0x8000>;
d-cache-line-size = <64>;
d-cache-sets = <256>;
next-level-cache = <&cluster_a57_l2>;
};
cpu5: cpu@1 {
@@ -114,6 +149,13 @@ cpu5: cpu@1 {
clock-frequency = <1900000000>;
operating-points-v2 = <&cluster_a57_opp_table>;
#cooling-cells = <2>;
i-cache-size = <0xc000>;
i-cache-line-size = <64>;
i-cache-sets = <256>;
d-cache-size = <0x8000>;
d-cache-line-size = <64>;
d-cache-sets = <256>;
next-level-cache = <&cluster_a57_l2>;
};
cpu6: cpu@2 {
@@ -124,6 +166,13 @@ cpu6: cpu@2 {
clock-frequency = <1900000000>;
operating-points-v2 = <&cluster_a57_opp_table>;
#cooling-cells = <2>;
i-cache-size = <0xc000>;
i-cache-line-size = <64>;
i-cache-sets = <256>;
d-cache-size = <0x8000>;
d-cache-line-size = <64>;
d-cache-sets = <256>;
next-level-cache = <&cluster_a57_l2>;
};
cpu7: cpu@3 {
@@ -134,6 +183,27 @@ cpu7: cpu@3 {
clock-frequency = <1900000000>;
operating-points-v2 = <&cluster_a57_opp_table>;
#cooling-cells = <2>;
i-cache-size = <0xc000>;
i-cache-line-size = <64>;
i-cache-sets = <256>;
d-cache-size = <0x8000>;
d-cache-line-size = <64>;
d-cache-sets = <256>;
next-level-cache = <&cluster_a57_l2>;
};
cluster_a57_l2: l2-cache0 {
compatible = "cache";
cache-size = <0x200000>;
cache-line-size = <64>;
cache-sets = <2048>;
};
cluster_a53_l2: l2-cache1 {
compatible = "cache";
cache-size = <0x40000>;
cache-line-size = <64>;
cache-sets = <256>;
};
};