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ARM: dts: lager: Enable SCIF_CLK frequency and pins

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Add and enable the external crystal for the SCIF_CLK and its pinctrl, to
be used by the Baud Rate Generator for External Clock (BRG) on (H)SCIF.

This increases the range and accuracy of supported baud rates.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
This commit is contained in:
Geert Uytterhoeven
2016-01-29 11:17:22 +01:00
committed by Simon Horman
parent 338f7ebf46
commit 1781460c9a
1 changed files with 13 additions and 0 deletions
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13
arch/arm/boot/dts/r8a7790-lager.dts
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@@ -291,6 +291,9 @@ &extal_clk {
};
&pfc {
pinctrl-0 = <&scif_clk_pins>;
pinctrl-names = "default";
du_pins: du {
renesas,groups = "du_rgb666", "du_sync_1", "du_clk_out_0";
renesas,function = "du";
@@ -301,6 +304,11 @@ scif0_pins: serial0 {
renesas,function = "scif0";
};
scif_clk_pins: scif_clk {
renesas,groups = "scif_clk";
renesas,function = "scif_clk";
};
ether_pins: ether {
renesas,groups = "eth_link", "eth_mdio", "eth_rmii";
renesas,function = "eth";
@@ -485,6 +493,11 @@ &scifa1 {
status = "okay";
};
&scif_clk {
clock-frequency = <14745600>;
status = "okay";
};
&msiof1 {
pinctrl-0 = <&msiof1_pins>;
pinctrl-names = "default";