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dt-bindings: memory: tegra264: Add full set of MC client IDs
Add the complete set of TEGRA264_MEMORY_CLIENT_* IDs exposed by the Tegra264 MC. Signed-off-by: Sumit Gupta <sumitg@nvidia.com> Link: https://patch.msgid.link/20260518124306.2071481-3-sumitg@nvidia.com Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
This commit is contained in:
Sumit Gupta
committed by
Krzysztof Kozlowski
Krzysztof Kozlowski
parent
c3ce114d81
commit
16868fd4b7
@@ -58,24 +58,108 @@
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* memory client IDs
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*/
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/* PTW read client mapped to SOC SMMU0 */
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#define TEGRA264_MEMORY_CLIENT_PTCR 0x00
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/* HOST1X read client */
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#define TEGRA264_MEMORY_CLIENT_HOST1XR 0x16
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#define TEGRA264_MEMORY_CLIENT_MPCORER 0x27
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/* Platform security (PSC) Read clients */
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#define TEGRA264_MEMORY_CLIENT_PSCR 0x33
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/* PSC Write clients */
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#define TEGRA264_MEMORY_CLIENT_PSCW 0x34
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/* ISP0 Read client */
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#define TEGRA264_MEMORY_CLIENT_ISP0R 0x37
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#define TEGRA264_MEMORY_CLIENT_MPCOREW 0x39
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/* ISP0 Write client */
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#define TEGRA264_MEMORY_CLIENT_ISP0W 0x44
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/* ISP1 Write client */
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#define TEGRA264_MEMORY_CLIENT_ISP1W 0x45
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/* ISP FALCON Read client */
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#define TEGRA264_MEMORY_CLIENT_ISPFALCONR 0x47
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/* ISP FALCON Write client */
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#define TEGRA264_MEMORY_CLIENT_ISPFALCONW 0x4f
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/* MGBE2 Read mccif */
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#define TEGRA264_MEMORY_CLIENT_MGBE2R 0x5c
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#define TEGRA264_MEMORY_CLIENT_OFAR2MC 0x5d
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#define TEGRA264_MEMORY_CLIENT_OFAW2MC 0x5e
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/* MGBE2 Write mccif */
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#define TEGRA264_MEMORY_CLIENT_MGBE2W 0x5f
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/* MGBE3 Read mccif */
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#define TEGRA264_MEMORY_CLIENT_MGBE3R 0x61
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/* MGBE3 Write mccif */
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#define TEGRA264_MEMORY_CLIENT_MGBE3W 0x65
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/* SEU1 Memory Read Client */
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#define TEGRA264_MEMORY_CLIENT_SEU1RD 0x68
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/* SEU1 Memory Write Client */
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#define TEGRA264_MEMORY_CLIENT_SEU1WR 0x69
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/* VIC read client */
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#define TEGRA264_MEMORY_CLIENT_VICR 0x6c
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/* VIC Write client */
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#define TEGRA264_MEMORY_CLIENT_VICW 0x6d
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/* VI R5 Write client */
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#define TEGRA264_MEMORY_CLIENT_VIW 0x72
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/* QSPI Read Client */
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#define TEGRA264_MEMORY_CLIENT_XSPI0R 0x75
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/* QSPI Write Client */
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#define TEGRA264_MEMORY_CLIENT_XSPI0W 0x76
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#define TEGRA264_MEMORY_CLIENT_NVDECSRD2MC 0x78
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#define TEGRA264_MEMORY_CLIENT_NVDECSWR2MC 0x79
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/* Audio processor(APE) Read client */
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#define TEGRA264_MEMORY_CLIENT_APER 0x7a
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/* Audio processor(APE) Write client */
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#define TEGRA264_MEMORY_CLIENT_APEW 0x7b
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/* SEU0 read client */
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#define TEGRA264_MEMORY_CLIENT_SER 0x80
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/* SEU0 write client */
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#define TEGRA264_MEMORY_CLIENT_SEW 0x81
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/* AXI AP and DFD/Coresight1-AUX0/1 Read clients both share the same interface on MSS */
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#define TEGRA264_MEMORY_CLIENT_AXIAPR 0x82
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/* AXI AP and DFD/Coresight1-AUX0/1 Write clients both share the same interface on MSS */
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#define TEGRA264_MEMORY_CLIENT_AXIAPW 0x83
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/* ETR or DFD/Coresight0 Read Client */
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#define TEGRA264_MEMORY_CLIENT_ETRR 0x84
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/* ETR or DFD/Coresight0 Write Client */
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#define TEGRA264_MEMORY_CLIENT_ETRW 0x85
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/* Security(tsec) Read client */
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#define TEGRA264_MEMORY_CLIENT_TSECR 0x86
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/* Security(tsec) Write client */
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#define TEGRA264_MEMORY_CLIENT_TSECW 0x87
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/* BPMP read client */
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#define TEGRA264_MEMORY_CLIENT_BPMPR 0x93
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/* BPMP write client */
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#define TEGRA264_MEMORY_CLIENT_BPMPW 0x94
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/* AON Read Client */
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#define TEGRA264_MEMORY_CLIENT_AONR 0x97
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/* AON write client */
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#define TEGRA264_MEMORY_CLIENT_AONW 0x98
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/* GPCDMA debug Read client */
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#define TEGRA264_MEMORY_CLIENT_GPCDMAR 0x99
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/* GPCDMA debug Write client */
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#define TEGRA264_MEMORY_CLIENT_GPCDMAW 0x9a
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/* Audio DMA Read client */
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#define TEGRA264_MEMORY_CLIENT_APEDMAR 0x9f
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/* Audio DMA Write client */
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#define TEGRA264_MEMORY_CLIENT_APEDMAW 0xa0
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/* mss internal memqual MIU0 reads */
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#define TEGRA264_MEMORY_CLIENT_MIU0R 0xa6
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/* mss internal memqual MIU0 writes */
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#define TEGRA264_MEMORY_CLIENT_MIU0W 0xa7
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/* mss internal memqual MIU1 reads */
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#define TEGRA264_MEMORY_CLIENT_MIU1R 0xa8
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/* mss internal memqual MIU1 writes */
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#define TEGRA264_MEMORY_CLIENT_MIU1W 0xa9
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/* mss internal memqual MIU2 reads */
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#define TEGRA264_MEMORY_CLIENT_MIU2R 0xae
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/* mss internal memqual MIU2 writes */
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#define TEGRA264_MEMORY_CLIENT_MIU2W 0xaf
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/* mss internal memqual MIU3 reads */
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#define TEGRA264_MEMORY_CLIENT_MIU3R 0xb0
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/* mss internal memqual MIU3 writes */
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#define TEGRA264_MEMORY_CLIENT_MIU3W 0xb1
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/* mss internal memqual MIU4 reads */
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#define TEGRA264_MEMORY_CLIENT_MIU4R 0xb2
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/* mss internal memqual MIU4 writes */
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#define TEGRA264_MEMORY_CLIENT_MIU4W 0xb3
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#define TEGRA264_MEMORY_CLIENT_GPUR02MC 0xb6
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#define TEGRA264_MEMORY_CLIENT_GPUW02MC 0xb7
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/* VI Falcon Read client */
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@@ -86,6 +170,8 @@
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#define TEGRA264_MEMORY_CLIENT_RCER 0xd2
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/* Write client of RCE */
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#define TEGRA264_MEMORY_CLIENT_RCEW 0xd3
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#define TEGRA264_MEMORY_CLIENT_NVENC1SRD2MC 0xd6
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#define TEGRA264_MEMORY_CLIENT_NVENC1SWR2MC 0xd7
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/* PCIE0/MSI Write clients */
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#define TEGRA264_MEMORY_CLIENT_PCIE0W 0xd9
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/* PCIE1/RPX4 Read clients */
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@@ -108,16 +194,140 @@
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#define TEGRA264_MEMORY_CLIENT_PCIE5R 0xe2
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/* PCIE5/DMX4 Write clients */
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#define TEGRA264_MEMORY_CLIENT_PCIE5W 0xe3
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/* mss internal memqual MIU5 reads */
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#define TEGRA264_MEMORY_CLIENT_MIU5R 0xfc
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/* mss internal memqual MIU5 writes */
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#define TEGRA264_MEMORY_CLIENT_MIU5W 0xfd
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/* mss internal memqual MIU6 writes */
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#define TEGRA264_MEMORY_CLIENT_MIU6W 0xff
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#define TEGRA264_MEMORY_CLIENT_RISTR 0x100
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#define TEGRA264_MEMORY_CLIENT_RISTW 0x101
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/* OESP (Pluton) Read client */
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#define TEGRA264_MEMORY_CLIENT_OESPR 0x102
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/* OESP (Pluton) Write client */
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#define TEGRA264_MEMORY_CLIENT_OESPW 0x103
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/* mss internal memqual MIU7 writes */
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#define TEGRA264_MEMORY_CLIENT_MIU7W 0x105
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/* mss internal memqual MIU8 reads */
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#define TEGRA264_MEMORY_CLIENT_MIU8R 0x106
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/* mss internal memqual MIU8 writes */
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#define TEGRA264_MEMORY_CLIENT_MIU8W 0x107
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/* mss internal memqual MIU9 reads */
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#define TEGRA264_MEMORY_CLIENT_MIU9R 0x108
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/* mss internal memqual MIU9 writes */
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#define TEGRA264_MEMORY_CLIENT_MIU9W 0x109
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/* HWPM Write Interface */
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#define TEGRA264_MEMORY_CLIENT_PMA0AWR 0x122
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#define TEGRA264_MEMORY_CLIENT_NVJPG1SRD2MC 0x123
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#define TEGRA264_MEMORY_CLIENT_NVJPG1SWR2MC 0x124
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/* CTW read client mapped to SMMU0 */
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#define TEGRA264_MEMORY_CLIENT_SMMU0CTWR 0x12e
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/* CMDQV read client mapped to SMMU0 */
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#define TEGRA264_MEMORY_CLIENT_SMMU0CMDQVR 0x12f
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/* CMDQV write client mapped to SMMU0 */
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#define TEGRA264_MEMORY_CLIENT_SMMU0CMDQVW 0x130
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/* EVNTQ write client mapped to SMMU0 */
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#define TEGRA264_MEMORY_CLIENT_SMMU0EVNTQW 0x131
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/* PTW read client mapped to SMMU1 */
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#define TEGRA264_MEMORY_CLIENT_SMMU1PTWR 0x132
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/* CTW read client mapped to SMMU1 */
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#define TEGRA264_MEMORY_CLIENT_SMMU1CTWR 0x134
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/* CMDQV read client mapped to SMMU1 */
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#define TEGRA264_MEMORY_CLIENT_SMMU1CMDQVR 0x135
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/* CMDQV write client mapped to SMMU1 */
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#define TEGRA264_MEMORY_CLIENT_SMMU1CMDQVW 0x136
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/* EVNTQ write client mapped to SMMU1 */
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#define TEGRA264_MEMORY_CLIENT_SMMU1EVNTQW 0x137
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/* PTW read client mapped to SMMU2 */
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#define TEGRA264_MEMORY_CLIENT_SMMU2PTWR 0x138
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/* CTW read client mapped to SMMU2 */
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#define TEGRA264_MEMORY_CLIENT_SMMU2CTWR 0x13a
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/* CMDQV read client mapped to SMMU2 */
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#define TEGRA264_MEMORY_CLIENT_SMMU2CMDQVR 0x13b
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/* CMDQV write client mapped to SMMU2 */
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#define TEGRA264_MEMORY_CLIENT_SMMU2CMDQVW 0x13c
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/* EVNTQ write client mapped to SMMU2 */
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#define TEGRA264_MEMORY_CLIENT_SMMU2EVNTQW 0x13d
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/* CMDQ read client mapped to SMMU0 */
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#define TEGRA264_MEMORY_CLIENT_SMMU0CMDQR 0x144
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/* CMDQ read client mapped to SMMU1 */
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#define TEGRA264_MEMORY_CLIENT_SMMU1CMDQR 0x145
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/* CMDQ read client mapped to SMMU2 */
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#define TEGRA264_MEMORY_CLIENT_SMMU2CMDQR 0x146
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/* Audio processor1(APE1) Read client */
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#define TEGRA264_MEMORY_CLIENT_APE1R 0x150
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/* Audio processor1(APE1) Write client */
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#define TEGRA264_MEMORY_CLIENT_APE1W 0x151
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/* UFS Read client */
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#define TEGRA264_MEMORY_CLIENT_UFSR 0x15c
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/* UFS write client */
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#define TEGRA264_MEMORY_CLIENT_UFSW 0x15d
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/* XUSB HOST Read Client */
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#define TEGRA264_MEMORY_CLIENT_XUSB_DEVR 0x166
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/* XUSB HOST Write Client */
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#define TEGRA264_MEMORY_CLIENT_XUSB_DEVW 0x167
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/* XUSB SS0 Read Client */
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#define TEGRA264_MEMORY_CLIENT_XUSB_DEV1R 0x168
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/* XUSB SS1 Write Client */
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#define TEGRA264_MEMORY_CLIENT_XUSB_DEV2W 0x169
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/* XUSB SS2 Read Client */
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#define TEGRA264_MEMORY_CLIENT_XUSB_DEV3R 0x16a
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/* XUSB SS2 Write Client */
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#define TEGRA264_MEMORY_CLIENT_XUSB_DEV3W 0x16b
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/* XUSB SS3 Read Client */
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#define TEGRA264_MEMORY_CLIENT_XUSB_DEV4R 0x16c
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/* XUSB SS3 Write Client */
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#define TEGRA264_MEMORY_CLIENT_XUSB_DEV4W 0x16d
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/* XUSB DEV Read Client */
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#define TEGRA264_MEMORY_CLIENT_XUSB_DEV5R 0x16e
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/* XUSB DEV Write Client */
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#define TEGRA264_MEMORY_CLIENT_XUSB_DEV5W 0x16f
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/* DCE Read client */
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#define TEGRA264_MEMORY_CLIENT_DCER 0x17a
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/* DCE Write client */
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#define TEGRA264_MEMORY_CLIENT_DCEW 0x17b
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/* HDA Read client */
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#define TEGRA264_MEMORY_CLIENT_HDAR 0x17c
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/* HDA Write client */
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#define TEGRA264_MEMORY_CLIENT_HDAW 0x17d
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/* DISPNISO read client */
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#define TEGRA264_MEMORY_CLIENT_DISPNISOR 0x17e
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/* DISPNISO write client */
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#define TEGRA264_MEMORY_CLIENT_DISPNISOW 0x17f
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/* XUSB SS0 Write Client */
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#define TEGRA264_MEMORY_CLIENT_XUSB_DEV1W 0x180
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/* XUSB SS1 Read Client */
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#define TEGRA264_MEMORY_CLIENT_XUSB_DEV2R 0x181
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/* Disp ISO Read Client */
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#define TEGRA264_MEMORY_CLIENT_DISPR 0x182
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/* MSSSEQ Read Client */
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#define TEGRA264_MEMORY_CLIENT_MSSSEQR 0x185
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/* MSSSEQ Write Client */
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#define TEGRA264_MEMORY_CLIENT_MSSSEQW 0x186
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/* PTW read client mapped to SMMU3 */
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#define TEGRA264_MEMORY_CLIENT_SMMU3PTWR 0x18b
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/* CTW read client mapped to SMMU3 */
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#define TEGRA264_MEMORY_CLIENT_SMMU3CTWR 0x18d
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/* CMDQV read client mapped to SMMU3 */
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#define TEGRA264_MEMORY_CLIENT_SMMU3CMDQVR 0x18e
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/* CMDQV write client mapped to SMMU3 */
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#define TEGRA264_MEMORY_CLIENT_SMMU3CMDQVW 0x18f
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/* EVNTQ write client mapped to SMMU3 */
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#define TEGRA264_MEMORY_CLIENT_SMMU3EVNTQW 0x190
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/* CMDQ read client mapped to SMMU3 */
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#define TEGRA264_MEMORY_CLIENT_SMMU3CMDQR 0x191
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/* PTW read client mapped to SMMU4 */
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#define TEGRA264_MEMORY_CLIENT_SMMU4PTWR 0x192
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/* CTW read client mapped to SMMU4 */
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#define TEGRA264_MEMORY_CLIENT_SMMU4CTWR 0x194
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/* CMDQV read client mapped to SMMU4 */
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#define TEGRA264_MEMORY_CLIENT_SMMU4CMDQVR 0x195
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/* CMDQV write client mapped to SMMU4 */
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#define TEGRA264_MEMORY_CLIENT_SMMU4CMDQVW 0x196
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/* EVNTQ write client mapped to SMMU4 */
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#define TEGRA264_MEMORY_CLIENT_SMMU4EVNTQW 0x197
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/* CMDQ read client mapped to SMMU4 */
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#define TEGRA264_MEMORY_CLIENT_SMMU4CMDQR 0x198
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/* MGBE0 Read mccif */
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#define TEGRA264_MEMORY_CLIENT_MGBE0R 0x1a2
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/* MGBE0 Write mccif */
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@@ -128,9 +338,86 @@
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#define TEGRA264_MEMORY_CLIENT_MGBE1W 0x1a5
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/* VI1 R5 Write client */
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#define TEGRA264_MEMORY_CLIENT_VI1W 0x1a6
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/* VI Falcon1 Read client */
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#define TEGRA264_MEMORY_CLIENT_VIFALCON1R 0x1a7
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/* VI Falcon1 Write client */
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#define TEGRA264_MEMORY_CLIENT_VIFALCON1W 0x1a8
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/* ISP FALCON1 Read client */
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#define TEGRA264_MEMORY_CLIENT_ISPFALCON1R 0x1a9
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/* ISP FALCON1 Write client */
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#define TEGRA264_MEMORY_CLIENT_ISPFALCON1W 0x1aa
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/* Read Client of RCE1 */
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#define TEGRA264_MEMORY_CLIENT_RCE1R 0x1ab
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/* Write client of RCE1 */
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#define TEGRA264_MEMORY_CLIENT_RCE1W 0x1ac
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/* SEU2 Read client */
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#define TEGRA264_MEMORY_CLIENT_SEU2R 0x1ad
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/* SEU2 Write client */
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#define TEGRA264_MEMORY_CLIENT_SEU2W 0x1ae
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/* SEU3 Read client */
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#define TEGRA264_MEMORY_CLIENT_SEU3R 0x1af
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/* SEU3 Write client */
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#define TEGRA264_MEMORY_CLIENT_SEU3W 0x1b0
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/* PVA0 Falcon Read mccif */
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#define TEGRA264_MEMORY_CLIENT_PVA0R 0x1b1
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/* PVA0 Falcon Write mccif */
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#define TEGRA264_MEMORY_CLIENT_PVA0W 0x1b2
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/* PVA1 Read mccif */
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#define TEGRA264_MEMORY_CLIENT_PVA1R 0x1b3
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/* PVA1 Write mccif */
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#define TEGRA264_MEMORY_CLIENT_PVA1W 0x1b4
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/* PVA2 Read mccif */
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#define TEGRA264_MEMORY_CLIENT_PVA2R 0x1b5
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/* PVA2 Write mccif */
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#define TEGRA264_MEMORY_CLIENT_PVA2W 0x1b6
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/* ISP3 Write client */
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#define TEGRA264_MEMORY_CLIENT_ISP3W 0x1b7
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/* ISP2 Read Client */
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#define TEGRA264_MEMORY_CLIENT_ISP2R 0x1b8
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/* ISP2 Write Client */
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#define TEGRA264_MEMORY_CLIENT_ISP2W 0x1b9
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/* EQOS Read mccif */
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#define TEGRA264_MEMORY_CLIENT_EQOSR 0x1bc
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/* EQOS Write mccif */
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#define TEGRA264_MEMORY_CLIENT_EQOSW 0x1bd
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/* FSI0 Read mccif */
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#define TEGRA264_MEMORY_CLIENT_FSI0R 0x1be
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/* FSI0 Write mccif */
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#define TEGRA264_MEMORY_CLIENT_FSI0W 0x1bf
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/* FSI1 Read mccif */
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#define TEGRA264_MEMORY_CLIENT_FSI1R 0x1c0
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/* FSI1 Write mccif */
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#define TEGRA264_MEMORY_CLIENT_FSI1W 0x1c1
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/* SDMMC0 Read mccif */
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#define TEGRA264_MEMORY_CLIENT_SDMMC0R 0x1c2
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/* SDMMC0 Write mccif */
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#define TEGRA264_MEMORY_CLIENT_SDMMC0W 0x1c3
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/* Strongbox (SB) read client */
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#define TEGRA264_MEMORY_CLIENT_SBR 0x1c6
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/* Strongbox (SB) write client */
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#define TEGRA264_MEMORY_CLIENT_SBW 0x1c7
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#define TEGRA264_MEMORY_CLIENT_HSS_MIU0R 0x1c8
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#define TEGRA264_MEMORY_CLIENT_HSS_MIU0W 0x1c9
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#define TEGRA264_MEMORY_CLIENT_HSS_MIU1R 0x1ca
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#define TEGRA264_MEMORY_CLIENT_HSS_MIU1W 0x1cb
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#define TEGRA264_MEMORY_CLIENT_HSS_MIU2R 0x1cc
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#define TEGRA264_MEMORY_CLIENT_HSS_MIU2W 0x1cd
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#define TEGRA264_MEMORY_CLIENT_HSS_MIU3R 0x1ce
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#define TEGRA264_MEMORY_CLIENT_HSS_MIU3W 0x1cf
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#define TEGRA264_MEMORY_CLIENT_HSS_MIU4R 0x1d0
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#define TEGRA264_MEMORY_CLIENT_HSS_MIU4W 0x1d1
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#define TEGRA264_MEMORY_CLIENT_HSS_MIU5R 0x1d2
|
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#define TEGRA264_MEMORY_CLIENT_HSS_MIU5W 0x1d3
|
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#define TEGRA264_MEMORY_CLIENT_HSS_MIU6R 0x1d4
|
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#define TEGRA264_MEMORY_CLIENT_HSS_MIU6W 0x1d5
|
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#define TEGRA264_MEMORY_CLIENT_HSS_MIU7R 0x1d6
|
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#define TEGRA264_MEMORY_CLIENT_HSS_MIU7W 0x1d7
|
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#define TEGRA264_MEMORY_CLIENT_GMMUR2MC 0x1d8
|
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#define TEGRA264_MEMORY_CLIENT_UCFELAR 0x1d9
|
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#define TEGRA264_MEMORY_CLIENT_UCFELAW 0x1da
|
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#define TEGRA264_MEMORY_CLIENT_SLCR 0x1db
|
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#define TEGRA264_MEMORY_CLIENT_SLCW 0x1dc
|
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#define TEGRA264_MEMORY_CLIENT_REMOTER 0x1dd
|
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#define TEGRA264_MEMORY_CLIENT_REMOTEW 0x1de
|
||||
|
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#endif /* DT_BINDINGS_MEMORY_NVIDIA_TEGRA264_H */
|
||||
|
||||
Reference in New Issue
Block a user