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drm/msm/adreno: Support AQE engine

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AQE (Applicaton Qrisc Engine) is a dedicated core inside CP which aides
in Raytracing related workloads. Add support for loading the AQE firmware
and initialize the necessary registers.

Signed-off-by: Akhil P Oommen <akhilpo@oss.qualcomm.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Patchwork: https://patchwork.freedesktop.org/patch/689020/
Message-ID: <20251118-kaana-gpu-support-v4-15-86eeb8e93fb6@oss.qualcomm.com>
Signed-off-by: Rob Clark <robin.clark@oss.qualcomm.com>
This commit is contained in:
Akhil P Oommen
2025-11-18 14:20:42 +05:30
committed by Rob Clark
parent 288a932008
commit 16201a1ee2
4 changed files with 28 additions and 0 deletions
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22
drivers/gpu/drm/msm/adreno/a6xx_gpu.c
View File

@@ -1118,6 +1118,23 @@ static int a6xx_ucode_load(struct msm_gpu *gpu)
}
}
if (!a6xx_gpu->aqe_bo && adreno_gpu->fw[ADRENO_FW_AQE]) {
a6xx_gpu->aqe_bo = adreno_fw_create_bo(gpu,
adreno_gpu->fw[ADRENO_FW_AQE], &a6xx_gpu->aqe_iova);
if (IS_ERR(a6xx_gpu->aqe_bo)) {
int ret = PTR_ERR(a6xx_gpu->aqe_bo);
a6xx_gpu->aqe_bo = NULL;
DRM_DEV_ERROR(&gpu->pdev->dev,
"Could not allocate AQE ucode: %d\n", ret);
return ret;
}
msm_gem_object_set_name(a6xx_gpu->aqe_bo, "aqefw");
}
/*
* Expanded APRIV and targets that support WHERE_AM_I both need a
* privileged buffer to store the RPTR shadow
@@ -2400,6 +2417,11 @@ static void a6xx_destroy(struct msm_gpu *gpu)
drm_gem_object_put(a6xx_gpu->sqe_bo);
}
if (a6xx_gpu->aqe_bo) {
msm_gem_unpin_iova(a6xx_gpu->aqe_bo, gpu->vm);
drm_gem_object_put(a6xx_gpu->aqe_bo);
}
if (a6xx_gpu->shadow_bo) {
msm_gem_unpin_iova(a6xx_gpu->shadow_bo, gpu->vm);
drm_gem_object_put(a6xx_gpu->shadow_bo);

2
drivers/gpu/drm/msm/adreno/a6xx_gpu.h
View File

@@ -59,6 +59,8 @@ struct a6xx_gpu {
struct drm_gem_object *sqe_bo;
uint64_t sqe_iova;
struct drm_gem_object *aqe_bo;
uint64_t aqe_iova;
struct msm_ringbuffer *cur_ring;
struct msm_ringbuffer *next_ring;

3
drivers/gpu/drm/msm/adreno/a8xx_gpu.c
View File

@@ -627,6 +627,9 @@ static int hw_init(struct msm_gpu *gpu)
goto out;
gpu_write64(gpu, REG_A8XX_CP_SQE_INSTR_BASE, a6xx_gpu->sqe_iova);
if (a6xx_gpu->aqe_iova)
gpu_write64(gpu, REG_A8XX_CP_AQE_INSTR_BASE_0, a6xx_gpu->aqe_iova);
/* Set the ringbuffer address */
gpu_write64(gpu, REG_A6XX_CP_RB_BASE, gpu->rb[0]->iova);
gpu_write(gpu, REG_A6XX_CP_RB_CNTL, MSM_GPU_RB_CNTL_DEFAULT);

1
drivers/gpu/drm/msm/adreno/adreno_gpu.h
View File

@@ -27,6 +27,7 @@ enum {
ADRENO_FW_PFP = 1,
ADRENO_FW_GMU = 1, /* a6xx */
ADRENO_FW_GPMU = 2,
ADRENO_FW_AQE = 3,
ADRENO_FW_MAX,
};