remoteproc: qcom_q6v5_mss: Add modem support on MSM8226

Add support for the external power block headswitch register needed by
MSM8226 and some other qcom platforms.

Co-developed-by: Matti Lehtimäki <matti.lehtimaki@gmail.com>
Signed-off-by: Matti Lehtimäki <matti.lehtimaki@gmail.com>
Reviewed-by: Stephan Gerhold <stephan.gerhold@linaro.org>
Signed-off-by: Luca Weiss <luca@lucaweiss.eu>
Link: https://lore.kernel.org/r/20250217-msm8226-modem-v5-5-2bc74b80e0ae@lucaweiss.eu
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
This commit is contained in:
Luca Weiss
2025-02-17 23:05:19 +01:00
committed by Bjorn Andersson
parent 4641840341
commit 155cd99d7d

View File

@@ -134,6 +134,11 @@
#define BOOT_FSM_TIMEOUT 10000
#define BHS_CHECK_MAX_LOOPS 200
/* External power block headswitch */
#define EXTERNAL_BHS_ON BIT(0)
#define EXTERNAL_BHS_STATUS BIT(4)
#define EXTERNAL_BHS_TIMEOUT_US 50
struct reg_info {
struct regulator *reg;
int uV;
@@ -161,6 +166,7 @@ struct rproc_hexagon_res {
bool has_mba_logs;
bool has_spare_reg;
bool has_qaccept_regs;
bool has_ext_bhs_reg;
bool has_ext_cntl_regs;
bool has_vq6;
};
@@ -180,6 +186,7 @@ struct q6v5 {
u32 halt_nc;
u32 halt_vq6;
u32 conn_box;
u32 ext_bhs;
u32 qaccept_mdm;
u32 qaccept_cx;
@@ -237,6 +244,7 @@ struct q6v5 {
bool has_mba_logs;
bool has_spare_reg;
bool has_qaccept_regs;
bool has_ext_bhs_reg;
bool has_ext_cntl_regs;
bool has_vq6;
u64 mpss_perm;
@@ -246,6 +254,7 @@ struct q6v5 {
};
enum {
MSS_MSM8226,
MSS_MSM8909,
MSS_MSM8916,
MSS_MSM8953,
@@ -415,6 +424,34 @@ static void q6v5_pds_disable(struct q6v5 *qproc, struct device **pds,
}
}
static int q6v5_external_bhs_enable(struct q6v5 *qproc)
{
u32 val;
int ret = 0;
/*
* Enable external power block headswitch and wait for it to
* stabilize
*/
regmap_set_bits(qproc->conn_map, qproc->ext_bhs, EXTERNAL_BHS_ON);
ret = regmap_read_poll_timeout(qproc->conn_map, qproc->ext_bhs,
val, val & EXTERNAL_BHS_STATUS,
1, EXTERNAL_BHS_TIMEOUT_US);
if (ret) {
dev_err(qproc->dev, "External BHS timed out\n");
ret = -ETIMEDOUT;
}
return ret;
}
static void q6v5_external_bhs_disable(struct q6v5 *qproc)
{
regmap_clear_bits(qproc->conn_map, qproc->ext_bhs, EXTERNAL_BHS_ON);
}
static int q6v5_xfer_mem_ownership(struct q6v5 *qproc, u64 *current_perm,
bool local, bool remote, phys_addr_t addr,
size_t size)
@@ -1112,11 +1149,17 @@ static int q6v5_mba_load(struct q6v5 *qproc)
goto disable_proxy_clk;
}
if (qproc->has_ext_bhs_reg) {
ret = q6v5_external_bhs_enable(qproc);
if (ret < 0)
goto disable_vdd;
}
ret = q6v5_clk_enable(qproc->dev, qproc->reset_clks,
qproc->reset_clk_count);
if (ret) {
dev_err(qproc->dev, "failed to enable reset clocks\n");
goto disable_vdd;
goto disable_ext_bhs;
}
ret = q6v5_reset_deassert(qproc);
@@ -1214,6 +1257,9 @@ static int q6v5_mba_load(struct q6v5 *qproc)
disable_reset_clks:
q6v5_clk_disable(qproc->dev, qproc->reset_clks,
qproc->reset_clk_count);
disable_ext_bhs:
if (qproc->has_ext_bhs_reg)
q6v5_external_bhs_disable(qproc);
disable_vdd:
q6v5_regulator_disable(qproc, qproc->active_regs,
qproc->active_reg_count);
@@ -1281,6 +1327,8 @@ static void q6v5_mba_reclaim(struct q6v5 *qproc)
qproc->reset_clk_count);
q6v5_clk_disable(qproc->dev, qproc->active_clks,
qproc->active_clk_count);
if (qproc->has_ext_bhs_reg)
q6v5_external_bhs_disable(qproc);
q6v5_regulator_disable(qproc, qproc->active_regs,
qproc->active_reg_count);
@@ -1750,6 +1798,23 @@ static int q6v5_init_mem(struct q6v5 *qproc, struct platform_device *pdev)
qproc->qaccept_axi = args.args[2];
}
if (qproc->has_ext_bhs_reg) {
ret = of_parse_phandle_with_fixed_args(pdev->dev.of_node,
"qcom,ext-bhs-reg",
1, 0, &args);
if (ret < 0) {
dev_err(&pdev->dev, "failed to parse ext-bhs-reg index 0\n");
return -EINVAL;
}
qproc->conn_map = syscon_node_to_regmap(args.np);
of_node_put(args.np);
if (IS_ERR(qproc->conn_map))
return PTR_ERR(qproc->conn_map);
qproc->ext_bhs = args.args[0];
}
if (qproc->has_ext_cntl_regs) {
ret = of_parse_phandle_with_fixed_args(pdev->dev.of_node,
"qcom,ext-regs",
@@ -2021,6 +2086,7 @@ static int q6v5_probe(struct platform_device *pdev)
platform_set_drvdata(pdev, qproc);
qproc->has_qaccept_regs = desc->has_qaccept_regs;
qproc->has_ext_bhs_reg = desc->has_ext_bhs_reg;
qproc->has_ext_cntl_regs = desc->has_ext_cntl_regs;
qproc->has_vq6 = desc->has_vq6;
qproc->has_spare_reg = desc->has_spare_reg;
@@ -2174,6 +2240,7 @@ static const struct rproc_hexagon_res sc7180_mss = {
.has_mba_logs = true,
.has_spare_reg = true,
.has_qaccept_regs = false,
.has_ext_bhs_reg = false,
.has_ext_cntl_regs = false,
.has_vq6 = false,
.version = MSS_SC7180,
@@ -2202,6 +2269,7 @@ static const struct rproc_hexagon_res sc7280_mss = {
.has_mba_logs = true,
.has_spare_reg = false,
.has_qaccept_regs = true,
.has_ext_bhs_reg = false,
.has_ext_cntl_regs = true,
.has_vq6 = true,
.version = MSS_SC7280,
@@ -2233,6 +2301,7 @@ static const struct rproc_hexagon_res sdm660_mss = {
.has_mba_logs = false,
.has_spare_reg = false,
.has_qaccept_regs = false,
.has_ext_bhs_reg = false,
.has_ext_cntl_regs = false,
.has_vq6 = false,
.version = MSS_SDM660,
@@ -2268,6 +2337,7 @@ static const struct rproc_hexagon_res sdm845_mss = {
.has_mba_logs = false,
.has_spare_reg = false,
.has_qaccept_regs = false,
.has_ext_bhs_reg = false,
.has_ext_cntl_regs = false,
.has_vq6 = false,
.version = MSS_SDM845,
@@ -2299,6 +2369,7 @@ static const struct rproc_hexagon_res msm8998_mss = {
.has_mba_logs = false,
.has_spare_reg = false,
.has_qaccept_regs = false,
.has_ext_bhs_reg = false,
.has_ext_cntl_regs = false,
.has_vq6 = false,
.version = MSS_MSM8998,
@@ -2337,6 +2408,7 @@ static const struct rproc_hexagon_res msm8996_mss = {
.has_mba_logs = false,
.has_spare_reg = false,
.has_qaccept_regs = false,
.has_ext_bhs_reg = false,
.has_ext_cntl_regs = false,
.has_vq6 = false,
.version = MSS_MSM8996,
@@ -2371,6 +2443,7 @@ static const struct rproc_hexagon_res msm8909_mss = {
.has_mba_logs = false,
.has_spare_reg = false,
.has_qaccept_regs = false,
.has_ext_bhs_reg = false,
.has_ext_cntl_regs = false,
.has_vq6 = false,
.version = MSS_MSM8909,
@@ -2416,6 +2489,7 @@ static const struct rproc_hexagon_res msm8916_mss = {
.has_mba_logs = false,
.has_spare_reg = false,
.has_qaccept_regs = false,
.has_ext_bhs_reg = false,
.has_ext_cntl_regs = false,
.has_vq6 = false,
.version = MSS_MSM8916,
@@ -2451,6 +2525,7 @@ static const struct rproc_hexagon_res msm8953_mss = {
.has_mba_logs = false,
.has_spare_reg = false,
.has_qaccept_regs = false,
.has_ext_bhs_reg = false,
.has_ext_cntl_regs = false,
.has_vq6 = false,
.version = MSS_MSM8953,
@@ -2503,13 +2578,53 @@ static const struct rproc_hexagon_res msm8974_mss = {
.has_mba_logs = false,
.has_spare_reg = false,
.has_qaccept_regs = false,
.has_ext_bhs_reg = false,
.has_ext_cntl_regs = false,
.has_vq6 = false,
.version = MSS_MSM8974,
};
static const struct rproc_hexagon_res msm8226_mss = {
.hexagon_mba_image = "mba.b00",
.proxy_supply = (struct qcom_mss_reg_res[]) {
{
.supply = "pll",
.uA = 100000,
},
{
.supply = "mx",
.uV = 1050000,
},
{}
},
.proxy_clk_names = (char*[]){
"xo",
NULL
},
.active_clk_names = (char*[]){
"iface",
"bus",
"mem",
NULL
},
.proxy_pd_names = (char*[]){
"cx",
NULL
},
.need_mem_protection = false,
.has_alt_reset = false,
.has_mba_logs = false,
.has_spare_reg = false,
.has_qaccept_regs = false,
.has_ext_bhs_reg = true,
.has_ext_cntl_regs = false,
.has_vq6 = false,
.version = MSS_MSM8226,
};
static const struct of_device_id q6v5_of_match[] = {
{ .compatible = "qcom,q6v5-pil", .data = &msm8916_mss},
{ .compatible = "qcom,msm8226-mss-pil", .data = &msm8226_mss},
{ .compatible = "qcom,msm8909-mss-pil", .data = &msm8909_mss},
{ .compatible = "qcom,msm8916-mss-pil", .data = &msm8916_mss},
{ .compatible = "qcom,msm8953-mss-pil", .data = &msm8953_mss},