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drm/amd/display: Remove redundant null checks

Browse Source 
The null checks are redundant as they were already dereferenced
previously, as reported by Coverity; therefore the null checks
are removed.

This fixes 7 REVERSE_INULL issues reported by Coverity.

Reviewed-by: Harry Wentland <harry.wentland@amd.com>
Acked-by: Hamza Mahfooz <hamza.mahfooz@amd.com>
Signed-off-by: Alex Hung <alex.hung@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Alex Hung
2024-06-07 11:20:36 -06:00
committed by Alex Deucher
parent 9e6da7b70b
commit 14f293e044
6 changed files with 54 additions and 61 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c
View File

@@ -553,7 +553,7 @@ static void dcn32_auto_dpm_test_log(
//
// AutoDPMTest: clk1:%d - clk2:%d - clk3:%d - clk4:%d\n"
////////////////////////////////////////////////////////////////////////////
if (new_clocks && active_pipe_count > 0 &&
if (active_pipe_count > 0 &&
new_clocks->dramclk_khz > 0 &&
new_clocks->fclk_khz > 0 &&
new_clocks->dcfclk_khz > 0 &&

4
drivers/gpu/drm/amd/display/dc/core/dc.c
View File

@@ -2640,7 +2640,7 @@ static enum surface_update_type det_surface_update(const struct dc *dc,
if (u->plane_info)
format = u->plane_info->format;
else if (u->surface)
else
format = u->surface->format;
if (dce_use_lut(format))
@@ -2741,7 +2741,7 @@ static enum surface_update_type check_update_surfaces_for_stream(
if (stream_update->mst_bw_update)
su_flags->bits.mst_bw = 1;
if (stream_update->stream && stream_update->stream->freesync_on_desktop &&
if (stream_update->stream->freesync_on_desktop &&
(stream_update->vrr_infopacket || stream_update->allow_freesync ||
stream_update->vrr_active_variable || stream_update->vrr_active_fixed))
su_flags->bits.fams_changed = 1;

2
drivers/gpu/drm/amd/display/dc/core/dc_resource.c
View File

@@ -2099,7 +2099,7 @@ int resource_get_odm_slice_dst_width(struct pipe_ctx *otg_master,
timing->h_border_right;
width = h_active / count;
if (otg_master->stream_res.tg && otg_master->stream)
if (otg_master->stream_res.tg)
two_pixel_alignment_required =
otg_master->stream_res.tg->funcs->is_two_pixels_per_container(timing) ||
/*

4
drivers/gpu/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c
View File

@@ -102,9 +102,7 @@ void dml21_apply_soc_bb_overrides(struct dml2_initialize_instance_in_out *dml_in
struct dml2_soc_state_table *dml_clk_table = &dml_soc_bb->clk_table;
/* override clocks if smu is present */
if (in_dc->clk_mgr &&
in_dc->clk_mgr->funcs->is_smu_present &&
in_dc->clk_mgr->funcs->is_smu_present(in_dc->clk_mgr)) {
if (in_dc->clk_mgr->funcs->is_smu_present && in_dc->clk_mgr->funcs->is_smu_present(in_dc->clk_mgr)) {
/* dcfclk */
if (dc_clk_table->num_entries_per_clk.num_dcfclk_levels) {
dml_clk_table->dcfclk.num_clk_values = dc_clk_table->num_entries_per_clk.num_dcfclk_levels;

8
drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c
View File

@@ -742,12 +742,10 @@ void dce110_edp_wait_for_hpd_ready(
return;
}
if (link != NULL) {
if (link->panel_config.pps.extra_t3_ms > 0) {
int extra_t3_in_ms = link->panel_config.pps.extra_t3_ms;
if (link->panel_config.pps.extra_t3_ms > 0) {
int extra_t3_in_ms = link->panel_config.pps.extra_t3_ms;
msleep(extra_t3_in_ms);
}
msleep(extra_t3_in_ms);
}
dal_gpio_open(hpd, GPIO_MODE_INTERRUPT);

95
drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c
View File

@@ -271,58 +271,55 @@ bool dcn32_apply_idle_power_optimizations(struct dc *dc, bool enable)
}
if (enable) {
if (dc->current_state) {
/* 1. Check no memory request case for CAB.
* If no memory request case, send CAB_ACTION NO_DF_REQ DMUB message
*/
if (dcn32_check_no_memory_request_for_cab(dc)) {
/* Enable no-memory-requests case */
memset(&cmd, 0, sizeof(cmd));
cmd.cab.header.type = DMUB_CMD__CAB_FOR_SS;
cmd.cab.header.sub_type = DMUB_CMD__CAB_NO_DCN_REQ;
cmd.cab.header.payload_bytes = sizeof(cmd.cab) - sizeof(cmd.cab.header);
/* 1. Check no memory request case for CAB.
* If no memory request case, send CAB_ACTION NO_DF_REQ DMUB message
*/
if (dcn32_check_no_memory_request_for_cab(dc)) {
/* Enable no-memory-requests case */
memset(&cmd, 0, sizeof(cmd));
cmd.cab.header.type = DMUB_CMD__CAB_FOR_SS;
cmd.cab.header.sub_type = DMUB_CMD__CAB_NO_DCN_REQ;
cmd.cab.header.payload_bytes = sizeof(cmd.cab) - sizeof(cmd.cab.header);
dc_wake_and_execute_dmub_cmd(dc->ctx, &cmd, DM_DMUB_WAIT_TYPE_NO_WAIT);
return true;
}
/* 2. Check if all surfaces can fit in CAB.
* If surfaces can fit into CAB, send CAB_ACTION_ALLOW DMUB message
* and configure HUBP's to fetch from MALL
*/
ways = dcn32_calculate_cab_allocation(dc, dc->current_state);
/* MALL not supported with Stereo3D or TMZ surface. If any plane is using stereo,
* or TMZ surface, don't try to enter MALL.
*/
for (i = 0; i < dc->current_state->stream_count; i++) {
for (j = 0; j < dc->current_state->stream_status[i].plane_count; j++) {
plane = dc->current_state->stream_status[i].plane_states[j];
if (plane->address.type == PLN_ADDR_TYPE_GRPH_STEREO ||
plane->address.tmz_surface) {
mall_ss_unsupported = true;
break;
}
}
if (mall_ss_unsupported)
break;
}
if (ways <= dc->caps.cache_num_ways && !mall_ss_unsupported) {
memset(&cmd, 0, sizeof(cmd));
cmd.cab.header.type = DMUB_CMD__CAB_FOR_SS;
cmd.cab.header.sub_type = DMUB_CMD__CAB_DCN_SS_FIT_IN_CAB;
cmd.cab.header.payload_bytes = sizeof(cmd.cab) - sizeof(cmd.cab.header);
cmd.cab.cab_alloc_ways = (uint8_t)ways;
dc_wake_and_execute_dmub_cmd(dc->ctx, &cmd, DM_DMUB_WAIT_TYPE_NO_WAIT);
return true;
}
dc_wake_and_execute_dmub_cmd(dc->ctx, &cmd, DM_DMUB_WAIT_TYPE_NO_WAIT);
return true;
}
/* 2. Check if all surfaces can fit in CAB.
* If surfaces can fit into CAB, send CAB_ACTION_ALLOW DMUB message
* and configure HUBP's to fetch from MALL
*/
ways = dcn32_calculate_cab_allocation(dc, dc->current_state);
/* MALL not supported with Stereo3D or TMZ surface. If any plane is using stereo,
* or TMZ surface, don't try to enter MALL.
*/
for (i = 0; i < dc->current_state->stream_count; i++) {
for (j = 0; j < dc->current_state->stream_status[i].plane_count; j++) {
plane = dc->current_state->stream_status[i].plane_states[j];
if (plane->address.type == PLN_ADDR_TYPE_GRPH_STEREO ||
plane->address.tmz_surface) {
mall_ss_unsupported = true;
break;
}
}
if (mall_ss_unsupported)
break;
}
if (ways <= dc->caps.cache_num_ways && !mall_ss_unsupported) {
memset(&cmd, 0, sizeof(cmd));
cmd.cab.header.type = DMUB_CMD__CAB_FOR_SS;
cmd.cab.header.sub_type = DMUB_CMD__CAB_DCN_SS_FIT_IN_CAB;
cmd.cab.header.payload_bytes = sizeof(cmd.cab) - sizeof(cmd.cab.header);
cmd.cab.cab_alloc_ways = (uint8_t)ways;
dc_wake_and_execute_dmub_cmd(dc->ctx, &cmd, DM_DMUB_WAIT_TYPE_NO_WAIT);
return true;
}
return false;
}