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arm64: dts: renesas: r9a09g047: Add WDT1-WDT3 nodes

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Add WDT1-WDT3 nodes to RZ/G3E ("R9A09G047") SoC DTSI.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20250115103858.104709-5-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
This commit is contained in:
Biju Das
2025-01-15 10:38:53 +00:00
committed by Geert Uytterhoeven
parent d33e65dc3c
commit 146a9b058e
1 changed files with 30 additions and 0 deletions
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30
arch/arm64/boot/dts/renesas/r9a09g047.dtsi
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@@ -175,6 +175,36 @@ scif0: serial@11c01400 {
status = "disabled";
};
wdt1: watchdog@14400000 {
compatible = "renesas,r9a09g047-wdt", "renesas,r9a09g057-wdt";
reg = <0 0x14400000 0 0x400>;
clocks = <&cpg CPG_MOD 0x4d>, <&cpg CPG_MOD 0x4e>;
clock-names = "pclk", "oscclk";
resets = <&cpg 0x76>;
power-domains = <&cpg>;
status = "disabled";
};
wdt2: watchdog@13000000 {
compatible = "renesas,r9a09g047-wdt", "renesas,r9a09g057-wdt";
reg = <0 0x13000000 0 0x400>;
clocks = <&cpg CPG_MOD 0x4f>, <&cpg CPG_MOD 0x50>;
clock-names = "pclk", "oscclk";
resets = <&cpg 0x77>;
power-domains = <&cpg>;
status = "disabled";
};
wdt3: watchdog@13000400 {
compatible = "renesas,r9a09g047-wdt", "renesas,r9a09g057-wdt";
reg = <0 0x13000400 0 0x400>;
clocks = <&cpg CPG_MOD 0x51>, <&cpg CPG_MOD 0x52>;
clock-names = "pclk", "oscclk";
resets = <&cpg 0x78>;
power-domains = <&cpg>;
status = "disabled";
};
i2c0: i2c@14400400 {
compatible = "renesas,riic-r9a09g047", "renesas,riic-r9a09g057";
reg = <0 0x14400400 0 0x400>;