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Merge tag 'ras_core_for_v6.11_rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip

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Pull RAS updates from Borislav Petkov:

 - A cleanup and a correction to the error injection driver to inject a
   MCA_MISC value only when one has actually been supplied by the user

* tag 'ras_core_for_v6.11_rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip:
  x86/mce: Remove unused variable and return value in machine_check_poll()
  x86/mce/inject: Only write MCA_MISC when a value has been supplied
This commit is contained in:
Linus Torvalds
2024-07-15 18:22:48 -07:00
parent 8028e290b6 5b9d292ea8
commit 1467b49869
3 changed files with 9 additions and 9 deletions
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3
arch/x86/include/asm/mce.h
View File

@@ -261,7 +261,8 @@ enum mcp_flags {
MCP_DONTLOG = BIT(2), /* only clear, don't log */
MCP_QUEUE_LOG = BIT(3), /* only queue to genpool */
};
bool machine_check_poll(enum mcp_flags flags, mce_banks_t *b);
void machine_check_poll(enum mcp_flags flags, mce_banks_t *b);
int mce_notify_irq(void);

7
arch/x86/kernel/cpu/mce/core.c
View File

@@ -677,10 +677,9 @@ DEFINE_PER_CPU(unsigned, mce_poll_count);
* is already totally * confused. In this case it's likely it will
* not fully execute the machine check handler either.
*/
bool machine_check_poll(enum mcp_flags flags, mce_banks_t *b)
void machine_check_poll(enum mcp_flags flags, mce_banks_t *b)
{
struct mce_bank *mce_banks = this_cpu_ptr(mce_banks_array);
bool error_seen = false;
struct mce m;
int i;
@@ -754,8 +753,6 @@ bool machine_check_poll(enum mcp_flags flags, mce_banks_t *b)
continue;
log_it:
error_seen = true;
if (flags & MCP_DONTLOG)
goto clear_it;
@@ -787,8 +784,6 @@ bool machine_check_poll(enum mcp_flags flags, mce_banks_t *b)
*/
sync_core();
return error_seen;
}
EXPORT_SYMBOL_GPL(machine_check_poll);

8
arch/x86/kernel/cpu/mce/inject.c
View File

@@ -487,12 +487,16 @@ static void prepare_msrs(void *info)
wrmsrl(MSR_AMD64_SMCA_MCx_ADDR(b), m.addr);
}
wrmsrl(MSR_AMD64_SMCA_MCx_MISC(b), m.misc);
wrmsrl(MSR_AMD64_SMCA_MCx_SYND(b), m.synd);
if (m.misc)
wrmsrl(MSR_AMD64_SMCA_MCx_MISC(b), m.misc);
} else {
wrmsrl(MSR_IA32_MCx_STATUS(b), m.status);
wrmsrl(MSR_IA32_MCx_ADDR(b), m.addr);
wrmsrl(MSR_IA32_MCx_MISC(b), m.misc);
if (m.misc)
wrmsrl(MSR_IA32_MCx_MISC(b), m.misc);
}
}