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Merge branch 'hns3-fixes'

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Guangbin Huang says:

====================
net: hns3: add some fixes for -net

This series adds some fixes for the HNS3 ethernet driver.
====================

Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
David S. Miller
2021-11-10 14:20:43 +00:00
parent 8f1bc38bbb 688db0c7a4
commit 1413ff132f
12 changed files with 149 additions and 134 deletions
Download Patch File Download Diff File Expand all files Collapse all files

7
drivers/net/ethernet/hisilicon/hns3/hns3_enet.c
View File

@@ -4210,6 +4210,13 @@ int hns3_clean_rx_ring(struct hns3_enet_ring *ring, int budget,
}
out:
/* sync head pointer before exiting, since hardware will calculate
* FBD number with head pointer
*/
if (unused_count > 0)
failure = failure ||
hns3_nic_alloc_rx_buffers(ring, unused_count);
return failure ? budget : recv_pkts;
}

1
drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.c
View File

@@ -483,6 +483,7 @@ static int hclge_firmware_compat_config(struct hclge_dev *hdev, bool en)
if (hnae3_dev_phy_imp_supported(hdev))
hnae3_set_bit(compat, HCLGE_PHY_IMP_EN_B, 1);
hnae3_set_bit(compat, HCLGE_MAC_STATS_EXT_EN_B, 1);
hnae3_set_bit(compat, HCLGE_SYNC_RX_RING_HEAD_EN_B, 1);
req->compat = cpu_to_le32(compat);
}

1
drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h
View File

@@ -1151,6 +1151,7 @@ struct hclge_query_ppu_pf_other_int_dfx_cmd {
#define HCLGE_NCSI_ERROR_REPORT_EN_B 1
#define HCLGE_PHY_IMP_EN_B 2
#define HCLGE_MAC_STATS_EXT_EN_B 3
#define HCLGE_SYNC_RX_RING_HEAD_EN_B 4
struct hclge_firmware_compat_cmd {
__le32 compat;
u8 rsv[20];

22
drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_dcb.c
View File

@@ -129,7 +129,7 @@ static int hclge_ets_sch_mode_validate(struct hclge_dev *hdev,
u32 total_ets_bw = 0;
u8 i;
for (i = 0; i < hdev->tc_max; i++) {
for (i = 0; i < HNAE3_MAX_TC; i++) {
switch (ets->tc_tsa[i]) {
case IEEE_8021QAZ_TSA_STRICT:
if (hdev->tm_info.tc_info[i].tc_sch_mode !=
@@ -286,28 +286,24 @@ static int hclge_ieee_setets(struct hnae3_handle *h, struct ieee_ets *ets)
static int hclge_ieee_getpfc(struct hnae3_handle *h, struct ieee_pfc *pfc)
{
u64 requests[HNAE3_MAX_TC], indications[HNAE3_MAX_TC];
struct hclge_vport *vport = hclge_get_vport(h);
struct hclge_dev *hdev = vport->back;
int ret;
u8 i;
memset(pfc, 0, sizeof(*pfc));
pfc->pfc_cap = hdev->pfc_max;
pfc->pfc_en = hdev->tm_info.pfc_en;
ret = hclge_pfc_tx_stats_get(hdev, requests);
if (ret)
ret = hclge_mac_update_stats(hdev);
if (ret) {
dev_err(&hdev->pdev->dev,
"failed to update MAC stats, ret = %d.\n", ret);
return ret;
ret = hclge_pfc_rx_stats_get(hdev, indications);
if (ret)
return ret;
for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
pfc->requests[i] = requests[i];
pfc->indications[i] = indications[i];
}
hclge_pfc_tx_stats_get(hdev, pfc->requests);
hclge_pfc_rx_stats_get(hdev, pfc->indications);
return 0;
}

106
drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
View File

@@ -26,8 +26,6 @@
#include "hclge_devlink.h"
#define HCLGE_NAME "hclge"
#define HCLGE_STATS_READ(p, offset) (*(u64 *)((u8 *)(p) + (offset)))
#define HCLGE_MAC_STATS_FIELD_OFF(f) (offsetof(struct hclge_mac_stats, f))
#define HCLGE_BUF_SIZE_UNIT 256U
#define HCLGE_BUF_MUL_BY 2
@@ -568,6 +566,16 @@ static int hclge_mac_query_reg_num(struct hclge_dev *hdev, u32 *reg_num)
struct hclge_desc desc;
int ret;
/* Driver needs total register number of both valid registers and
* reserved registers, but the old firmware only returns number
* of valid registers in device V2. To be compatible with these
* devices, driver uses a fixed value.
*/
if (hdev->ae_dev->dev_version == HNAE3_DEVICE_VERSION_V2) {
*reg_num = HCLGE_MAC_STATS_MAX_NUM_V1;
return 0;
}
hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_MAC_REG_NUM, true);
ret = hclge_cmd_send(&hdev->hw, &desc, 1);
if (ret) {
@@ -587,7 +595,7 @@ static int hclge_mac_query_reg_num(struct hclge_dev *hdev, u32 *reg_num)
return 0;
}
static int hclge_mac_update_stats(struct hclge_dev *hdev)
int hclge_mac_update_stats(struct hclge_dev *hdev)
{
/* The firmware supports the new statistics acquisition method */
if (hdev->ae_dev->dev_specs.mac_stats_num)
@@ -2581,7 +2589,7 @@ static int hclge_init_roce_base_info(struct hclge_vport *vport)
if (hdev->num_msi < hdev->num_nic_msi + hdev->num_roce_msi)
return -EINVAL;
roce->rinfo.base_vector = hdev->roce_base_vector;
roce->rinfo.base_vector = hdev->num_nic_msi;
roce->rinfo.netdev = nic->kinfo.netdev;
roce->rinfo.roce_io_base = hdev->hw.io_base;
@@ -2617,10 +2625,6 @@ static int hclge_init_msi(struct hclge_dev *hdev)
hdev->num_msi = vectors;
hdev->num_msi_left = vectors;
hdev->base_msi_vector = pdev->irq;
hdev->roce_base_vector = hdev->base_msi_vector +
hdev->num_nic_msi;
hdev->vector_status = devm_kcalloc(&pdev->dev, hdev->num_msi,
sizeof(u16), GFP_KERNEL);
if (!hdev->vector_status) {
@@ -8949,8 +8953,11 @@ int hclge_add_mc_addr_common(struct hclge_vport *vport,
err_no_space:
/* if already overflow, not to print each time */
if (!(vport->overflow_promisc_flags & HNAE3_OVERFLOW_MPE))
if (!(vport->overflow_promisc_flags & HNAE3_OVERFLOW_MPE)) {
vport->overflow_promisc_flags |= HNAE3_OVERFLOW_MPE;
dev_err(&hdev->pdev->dev, "mc mac vlan table is full\n");
}
return -ENOSPC;
}
@@ -9006,12 +9013,17 @@ int hclge_rm_mc_addr_common(struct hclge_vport *vport,
static void hclge_sync_vport_mac_list(struct hclge_vport *vport,
struct list_head *list,
int (*sync)(struct hclge_vport *,
const unsigned char *))
enum HCLGE_MAC_ADDR_TYPE mac_type)
{
int (*sync)(struct hclge_vport *vport, const unsigned char *addr);
struct hclge_mac_node *mac_node, *tmp;
int ret;
if (mac_type == HCLGE_MAC_ADDR_UC)
sync = hclge_add_uc_addr_common;
else
sync = hclge_add_mc_addr_common;
list_for_each_entry_safe(mac_node, tmp, list, node) {
ret = sync(vport, mac_node->mac_addr);
if (!ret) {
@@ -9023,8 +9035,13 @@ static void hclge_sync_vport_mac_list(struct hclge_vport *vport,
/* If one unicast mac address is existing in hardware,
* we need to try whether other unicast mac addresses
* are new addresses that can be added.
* Multicast mac address can be reusable, even though
* there is no space to add new multicast mac address,
* we should check whether other mac addresses are
* existing in hardware for reuse.
*/
if (ret != -EEXIST)
if ((mac_type == HCLGE_MAC_ADDR_UC && ret != -EEXIST) ||
(mac_type == HCLGE_MAC_ADDR_MC && ret != -ENOSPC))
break;
}
}
@@ -9032,12 +9049,17 @@ static void hclge_sync_vport_mac_list(struct hclge_vport *vport,
static void hclge_unsync_vport_mac_list(struct hclge_vport *vport,
struct list_head *list,
int (*unsync)(struct hclge_vport *,
const unsigned char *))
enum HCLGE_MAC_ADDR_TYPE mac_type)
{
int (*unsync)(struct hclge_vport *vport, const unsigned char *addr);
struct hclge_mac_node *mac_node, *tmp;
int ret;
if (mac_type == HCLGE_MAC_ADDR_UC)
unsync = hclge_rm_uc_addr_common;
else
unsync = hclge_rm_mc_addr_common;
list_for_each_entry_safe(mac_node, tmp, list, node) {
ret = unsync(vport, mac_node->mac_addr);
if (!ret || ret == -ENOENT) {
@@ -9168,17 +9190,8 @@ static void hclge_sync_vport_mac_table(struct hclge_vport *vport,
spin_unlock_bh(&vport->mac_list_lock);
/* delete first, in order to get max mac table space for adding */
if (mac_type == HCLGE_MAC_ADDR_UC) {
hclge_unsync_vport_mac_list(vport, &tmp_del_list,
hclge_rm_uc_addr_common);
hclge_sync_vport_mac_list(vport, &tmp_add_list,
hclge_add_uc_addr_common);
} else {
hclge_unsync_vport_mac_list(vport, &tmp_del_list,
hclge_rm_mc_addr_common);
hclge_sync_vport_mac_list(vport, &tmp_add_list,
hclge_add_mc_addr_common);
}
hclge_unsync_vport_mac_list(vport, &tmp_del_list, mac_type);
hclge_sync_vport_mac_list(vport, &tmp_add_list, mac_type);
/* if some mac addresses were added/deleted fail, move back to the
* mac_list, and retry at next time.
@@ -9337,12 +9350,7 @@ static void hclge_uninit_vport_mac_list(struct hclge_vport *vport,
spin_unlock_bh(&vport->mac_list_lock);
if (mac_type == HCLGE_MAC_ADDR_UC)
hclge_unsync_vport_mac_list(vport, &tmp_del_list,
hclge_rm_uc_addr_common);
else
hclge_unsync_vport_mac_list(vport, &tmp_del_list,
hclge_rm_mc_addr_common);
hclge_unsync_vport_mac_list(vport, &tmp_del_list, mac_type);
if (!list_empty(&tmp_del_list))
dev_warn(&hdev->pdev->dev,
@@ -9410,36 +9418,6 @@ static int hclge_get_mac_ethertype_cmd_status(struct hclge_dev *hdev,
return return_status;
}
static bool hclge_check_vf_mac_exist(struct hclge_vport *vport, int vf_idx,
u8 *mac_addr)
{
struct hclge_mac_vlan_tbl_entry_cmd req;
struct hclge_dev *hdev = vport->back;
struct hclge_desc desc;
u16 egress_port = 0;
int i;
if (is_zero_ether_addr(mac_addr))
return false;
memset(&req, 0, sizeof(req));
hnae3_set_field(egress_port, HCLGE_MAC_EPORT_VFID_M,
HCLGE_MAC_EPORT_VFID_S, vport->vport_id);
req.egress_port = cpu_to_le16(egress_port);
hclge_prepare_mac_addr(&req, mac_addr, false);
if (hclge_lookup_mac_vlan_tbl(vport, &req, &desc, false) != -ENOENT)
return true;
vf_idx += HCLGE_VF_VPORT_START_NUM;
for (i = HCLGE_VF_VPORT_START_NUM; i < hdev->num_alloc_vport; i++)
if (i != vf_idx &&
ether_addr_equal(mac_addr, hdev->vport[i].vf_info.mac))
return true;
return false;
}
static int hclge_set_vf_mac(struct hnae3_handle *handle, int vf,
u8 *mac_addr)
{
@@ -9457,12 +9435,6 @@ static int hclge_set_vf_mac(struct hnae3_handle *handle, int vf,
return 0;
}
if (hclge_check_vf_mac_exist(vport, vf, mac_addr)) {
dev_err(&hdev->pdev->dev, "Specified MAC(=%pM) exists!\n",
mac_addr);
return -EEXIST;
}
ether_addr_copy(vport->vf_info.mac, mac_addr);
if (test_bit(HCLGE_VPORT_STATE_ALIVE, &vport->state)) {

8
drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h
View File

@@ -404,7 +404,7 @@ struct hclge_tm_info {
};
/* max number of mac statistics on each version */
#define HCLGE_MAC_STATS_MAX_NUM_V1 84
#define HCLGE_MAC_STATS_MAX_NUM_V1 87
#define HCLGE_MAC_STATS_MAX_NUM_V2 105
struct hclge_comm_stats_str {
@@ -852,6 +852,9 @@ struct hclge_vf_vlan_cfg {
(y) = (_k_ ^ ~_v_) & (_k_); \
} while (0)
#define HCLGE_MAC_STATS_FIELD_OFF(f) (offsetof(struct hclge_mac_stats, f))
#define HCLGE_STATS_READ(p, offset) (*(u64 *)((u8 *)(p) + (offset)))
#define HCLGE_MAC_TNL_LOG_SIZE 8
#define HCLGE_VPORT_NUM 256
struct hclge_dev {
@@ -904,12 +907,10 @@ struct hclge_dev {
u16 num_msi;
u16 num_msi_left;
u16 num_msi_used;
u32 base_msi_vector;
u16 *vector_status;
int *vector_irq;
u16 num_nic_msi; /* Num of nic vectors for this PF */
u16 num_roce_msi; /* Num of roce vectors for this PF */
int roce_base_vector;
unsigned long service_timer_period;
unsigned long service_timer_previous;
@@ -1168,4 +1169,5 @@ void hclge_inform_vf_promisc_info(struct hclge_vport *vport);
int hclge_dbg_dump_rst_info(struct hclge_dev *hdev, char *buf, int len);
int hclge_push_vf_link_status(struct hclge_vport *vport);
int hclge_enable_vport_vlan_filter(struct hclge_vport *vport, bool request_en);
int hclge_mac_update_stats(struct hclge_dev *hdev);
#endif

79
drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_tm.c
View File

@@ -113,50 +113,50 @@ static int hclge_shaper_para_calc(u32 ir, u8 shaper_level,
return 0;
}
static int hclge_pfc_stats_get(struct hclge_dev *hdev,
enum hclge_opcode_type opcode, u64 *stats)
static const u16 hclge_pfc_tx_stats_offset[] = {
HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri0_pkt_num),
HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri1_pkt_num),
HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri2_pkt_num),
HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri3_pkt_num),
HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri4_pkt_num),
HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri5_pkt_num),
HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri6_pkt_num),
HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri7_pkt_num)
};
static const u16 hclge_pfc_rx_stats_offset[] = {
HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri0_pkt_num),
HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri1_pkt_num),
HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri2_pkt_num),
HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri3_pkt_num),
HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri4_pkt_num),
HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri5_pkt_num),
HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri6_pkt_num),
HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri7_pkt_num)
};
static void hclge_pfc_stats_get(struct hclge_dev *hdev, bool tx, u64 *stats)
{
struct hclge_desc desc[HCLGE_TM_PFC_PKT_GET_CMD_NUM];
int ret, i, j;
const u16 *offset;
int i;
if (!(opcode == HCLGE_OPC_QUERY_PFC_RX_PKT_CNT ||
opcode == HCLGE_OPC_QUERY_PFC_TX_PKT_CNT))
return -EINVAL;
if (tx)
offset = hclge_pfc_tx_stats_offset;
else
offset = hclge_pfc_rx_stats_offset;
for (i = 0; i < HCLGE_TM_PFC_PKT_GET_CMD_NUM - 1; i++) {
hclge_cmd_setup_basic_desc(&desc[i], opcode, true);
desc[i].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
}
hclge_cmd_setup_basic_desc(&desc[i], opcode, true);
ret = hclge_cmd_send(&hdev->hw, desc, HCLGE_TM_PFC_PKT_GET_CMD_NUM);
if (ret)
return ret;
for (i = 0; i < HCLGE_TM_PFC_PKT_GET_CMD_NUM; i++) {
struct hclge_pfc_stats_cmd *pfc_stats =
(struct hclge_pfc_stats_cmd *)desc[i].data;
for (j = 0; j < HCLGE_TM_PFC_NUM_GET_PER_CMD; j++) {
u32 index = i * HCLGE_TM_PFC_PKT_GET_CMD_NUM + j;
if (index < HCLGE_MAX_TC_NUM)
stats[index] =
le64_to_cpu(pfc_stats->pkt_num[j]);
}
}
return 0;
for (i = 0; i < HCLGE_MAX_TC_NUM; i++)
stats[i] = HCLGE_STATS_READ(&hdev->mac_stats, offset[i]);
}
int hclge_pfc_rx_stats_get(struct hclge_dev *hdev, u64 *stats)
void hclge_pfc_rx_stats_get(struct hclge_dev *hdev, u64 *stats)
{
return hclge_pfc_stats_get(hdev, HCLGE_OPC_QUERY_PFC_RX_PKT_CNT, stats);
hclge_pfc_stats_get(hdev, false, stats);
}
int hclge_pfc_tx_stats_get(struct hclge_dev *hdev, u64 *stats)
void hclge_pfc_tx_stats_get(struct hclge_dev *hdev, u64 *stats)
{
return hclge_pfc_stats_get(hdev, HCLGE_OPC_QUERY_PFC_TX_PKT_CNT, stats);
hclge_pfc_stats_get(hdev, true, stats);
}
int hclge_mac_pause_en_cfg(struct hclge_dev *hdev, bool tx, bool rx)
@@ -1123,7 +1123,6 @@ static int hclge_tm_pri_tc_base_dwrr_cfg(struct hclge_dev *hdev)
static int hclge_tm_ets_tc_dwrr_cfg(struct hclge_dev *hdev)
{
#define DEFAULT_TC_WEIGHT 1
#define DEFAULT_TC_OFFSET 14
struct hclge_ets_tc_weight_cmd *ets_weight;
@@ -1136,13 +1135,7 @@ static int hclge_tm_ets_tc_dwrr_cfg(struct hclge_dev *hdev)
for (i = 0; i < HNAE3_MAX_TC; i++) {
struct hclge_pg_info *pg_info;
ets_weight->tc_weight[i] = DEFAULT_TC_WEIGHT;
if (!(hdev->hw_tc_map & BIT(i)))
continue;
pg_info =
&hdev->tm_info.pg_info[hdev->tm_info.tc_info[i].pgid];
pg_info = &hdev->tm_info.pg_info[hdev->tm_info.tc_info[i].pgid];
ets_weight->tc_weight[i] = pg_info->tc_dwrr[i];
}

4
drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_tm.h
View File

@@ -228,8 +228,8 @@ int hclge_tm_dwrr_cfg(struct hclge_dev *hdev);
int hclge_tm_init_hw(struct hclge_dev *hdev, bool init);
int hclge_mac_pause_en_cfg(struct hclge_dev *hdev, bool tx, bool rx);
int hclge_pause_addr_cfg(struct hclge_dev *hdev, const u8 *mac_addr);
int hclge_pfc_rx_stats_get(struct hclge_dev *hdev, u64 *stats);
int hclge_pfc_tx_stats_get(struct hclge_dev *hdev, u64 *stats);
void hclge_pfc_rx_stats_get(struct hclge_dev *hdev, u64 *stats);
void hclge_pfc_tx_stats_get(struct hclge_dev *hdev, u64 *stats);
int hclge_tm_qs_shaper_cfg(struct hclge_vport *vport, int max_tx_rate);
int hclge_tm_get_qset_num(struct hclge_dev *hdev, u16 *qset_num);
int hclge_tm_get_pri_num(struct hclge_dev *hdev, u8 *pri_num);

32
drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_cmd.c
View File

@@ -434,8 +434,28 @@ int hclgevf_cmd_queue_init(struct hclgevf_dev *hdev)
return ret;
}
static int hclgevf_firmware_compat_config(struct hclgevf_dev *hdev, bool en)
{
struct hclgevf_firmware_compat_cmd *req;
struct hclgevf_desc desc;
u32 compat = 0;
hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_IMP_COMPAT_CFG, false);
if (en) {
req = (struct hclgevf_firmware_compat_cmd *)desc.data;
hnae3_set_bit(compat, HCLGEVF_SYNC_RX_RING_HEAD_EN_B, 1);
req->compat = cpu_to_le32(compat);
}
return hclgevf_cmd_send(&hdev->hw, &desc, 1);
}
int hclgevf_cmd_init(struct hclgevf_dev *hdev)
{
struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev);
int ret;
spin_lock_bh(&hdev->hw.cmq.csq.lock);
@@ -484,6 +504,17 @@ int hclgevf_cmd_init(struct hclgevf_dev *hdev)
hnae3_get_field(hdev->fw_version, HNAE3_FW_VERSION_BYTE0_MASK,
HNAE3_FW_VERSION_BYTE0_SHIFT));
if (ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V3) {
/* ask the firmware to enable some features, driver can work
* without it.
*/
ret = hclgevf_firmware_compat_config(hdev, true);
if (ret)
dev_warn(&hdev->pdev->dev,
"Firmware compatible features not enabled(%d).\n",
ret);
}
return 0;
err_cmd_init:
@@ -508,6 +539,7 @@ static void hclgevf_cmd_uninit_regs(struct hclgevf_hw *hw)
void hclgevf_cmd_uninit(struct hclgevf_dev *hdev)
{
hclgevf_firmware_compat_config(hdev, false);
set_bit(HCLGEVF_STATE_CMD_DISABLE, &hdev->state);
/* wait to ensure that the firmware completes the possible left
* over commands.

9
drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_cmd.h
View File

@@ -15,6 +15,12 @@
struct hclgevf_hw;
struct hclgevf_dev;
#define HCLGEVF_SYNC_RX_RING_HEAD_EN_B 4
struct hclgevf_firmware_compat_cmd {
__le32 compat;
u8 rsv[20];
};
struct hclgevf_desc {
__le16 opcode;
__le16 flag;
@@ -107,6 +113,9 @@ enum hclgevf_opcode_type {
HCLGEVF_OPC_RSS_TC_MODE = 0x0D08,
/* Mailbox cmd */
HCLGEVF_OPC_MBX_VF_TO_PF = 0x2001,
/* IMP stats command */
HCLGEVF_OPC_IMP_COMPAT_CFG = 0x701A,
};
#define HCLGEVF_TQP_REG_OFFSET 0x80000

10
drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_main.c
View File

@@ -2557,7 +2557,7 @@ static int hclgevf_init_roce_base_info(struct hclgevf_dev *hdev)
hdev->num_msi_left == 0)
return -EINVAL;
roce->rinfo.base_vector = hdev->roce_base_vector;
roce->rinfo.base_vector = hdev->roce_base_msix_offset;
roce->rinfo.netdev = nic->kinfo.netdev;
roce->rinfo.roce_io_base = hdev->hw.io_base;
@@ -2823,9 +2823,6 @@ static int hclgevf_init_msi(struct hclgevf_dev *hdev)
hdev->num_msi = vectors;
hdev->num_msi_left = vectors;
hdev->base_msi_vector = pdev->irq;
hdev->roce_base_vector = pdev->irq + hdev->roce_base_msix_offset;
hdev->vector_status = devm_kcalloc(&pdev->dev, hdev->num_msi,
sizeof(u16), GFP_KERNEL);
if (!hdev->vector_status) {
@@ -3013,7 +3010,10 @@ static void hclgevf_uninit_client_instance(struct hnae3_client *client,
/* un-init roce, if it exists */
if (hdev->roce_client) {
while (test_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state))
msleep(HCLGEVF_WAIT_RESET_DONE);
clear_bit(HCLGEVF_STATE_ROCE_REGISTERED, &hdev->state);
hdev->roce_client->ops->uninit_instance(&hdev->roce, 0);
hdev->roce_client = NULL;
hdev->roce.client = NULL;
@@ -3022,6 +3022,8 @@ static void hclgevf_uninit_client_instance(struct hnae3_client *client,
/* un-init nic/unic, if this was not called by roce client */
if (client->ops->uninit_instance && hdev->nic_client &&
client->type != HNAE3_CLIENT_ROCE) {
while (test_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state))
msleep(HCLGEVF_WAIT_RESET_DONE);
clear_bit(HCLGEVF_STATE_NIC_REGISTERED, &hdev->state);
client->ops->uninit_instance(&hdev->nic, 0);

4
drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_main.h
View File

@@ -109,6 +109,8 @@
#define HCLGEVF_VF_RST_ING 0x07008
#define HCLGEVF_VF_RST_ING_BIT BIT(16)
#define HCLGEVF_WAIT_RESET_DONE 100
#define HCLGEVF_RSS_IND_TBL_SIZE 512
#define HCLGEVF_RSS_SET_BITMAP_MSK 0xffff
#define HCLGEVF_RSS_KEY_SIZE 40
@@ -308,8 +310,6 @@ struct hclgevf_dev {
u16 num_nic_msix; /* Num of nic vectors for this VF */
u16 num_roce_msix; /* Num of roce vectors for this VF */
u16 roce_base_msix_offset;
int roce_base_vector;
u32 base_msi_vector;
u16 *vector_status;
int *vector_irq;