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drm/i915/adl_p: Don't config MBUS and DBUF during display initialization

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Alderlake-P don't have programing sequences for MBUS or DBUF during
display initializaiton, instead it requires programing to those
registers during modeset because it to depend on the pipes left
enabled.

Bspec: 49213
Cc: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Signed-off-by: Clinton Taylor <Clinton.A.Taylor@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20210519000625.3184321-7-lucas.demarchi@intel.com
This commit is contained in:
José Roberto de Souza
2021-05-18 17:06:14 -07:00
committed by Lucas De Marchi
parent 55ce306c2a
commit 14076e4645
1 changed files with 6 additions and 0 deletions
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6
drivers/gpu/drm/i915/display/intel_display_power.c
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@@ -5245,6 +5245,9 @@ static void gen12_dbuf_slices_config(struct drm_i915_private *dev_priv)
{
enum dbuf_slice slice;
if (IS_ALDERLAKE_P(dev_priv))
return;
for_each_dbuf_slice(dev_priv, slice)
intel_de_rmw(dev_priv, DBUF_CTL_S(slice),
DBUF_TRACKER_STATE_SERVICE_MASK,
@@ -5256,6 +5259,9 @@ static void icl_mbus_init(struct drm_i915_private *dev_priv)
unsigned long abox_regs = INTEL_INFO(dev_priv)->abox_mask;
u32 mask, val, i;
if (IS_ALDERLAKE_P(dev_priv))
return;
mask = MBUS_ABOX_BT_CREDIT_POOL1_MASK |
MBUS_ABOX_BT_CREDIT_POOL2_MASK |
MBUS_ABOX_B_CREDIT_MASK |