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drm/amdgpu/mes11: allocate hw_resource_1 buffer once

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Allocate the buffer at sw init time so we don't alloc
and free it for every suspend/resume or reset cycle.

Reviewed-by: Shaoyun.liu <shaouyun.liu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Alex Deucher
2025-02-14 10:11:17 -05:00
parent 196222dccb
commit 13d68ae651
1 changed files with 24 additions and 26 deletions
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50
drivers/gpu/drm/amd/amdgpu/mes_v11_0.c
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@@ -64,6 +64,7 @@ static int mes_v11_0_kiq_hw_fini(struct amdgpu_device *adev);
#define MES_EOP_SIZE 2048
#define GFX_MES_DRAM_SIZE 0x80000
#define MES11_HW_RESOURCE_1_SIZE (128 * AMDGPU_GPU_PAGE_SIZE)
static void mes_v11_0_ring_set_wptr(struct amdgpu_ring *ring)
{
@@ -732,11 +733,6 @@ static int mes_v11_0_set_hw_resources(struct amdgpu_mes *mes)
static int mes_v11_0_set_hw_resources_1(struct amdgpu_mes *mes)
{
unsigned int hw_rsrc_size = 128 * AMDGPU_GPU_PAGE_SIZE;
/* add a page for the cleaner shader fence */
unsigned int alloc_size = hw_rsrc_size + AMDGPU_GPU_PAGE_SIZE;
int ret = 0;
struct amdgpu_device *adev = mes->adev;
union MESAPI_SET_HW_RESOURCES_1 mes_set_hw_res_pkt;
memset(&mes_set_hw_res_pkt, 0, sizeof(mes_set_hw_res_pkt));
@@ -744,21 +740,10 @@ static int mes_v11_0_set_hw_resources_1(struct amdgpu_mes *mes)
mes_set_hw_res_pkt.header.opcode = MES_SCH_API_SET_HW_RSRC_1;
mes_set_hw_res_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS;
mes_set_hw_res_pkt.enable_mes_info_ctx = 1;
ret = amdgpu_bo_create_kernel(adev, alloc_size, PAGE_SIZE,
AMDGPU_GEM_DOMAIN_VRAM,
&mes->resource_1,
&mes->resource_1_gpu_addr,
&mes->resource_1_addr);
if (ret) {
dev_err(adev->dev, "(%d) failed to create mes resource_1 bo\n", ret);
return ret;
}
mes_set_hw_res_pkt.mes_info_ctx_mc_addr = mes->resource_1_gpu_addr;
mes_set_hw_res_pkt.mes_info_ctx_size = hw_rsrc_size;
mes_set_hw_res_pkt.mes_info_ctx_size = MES11_HW_RESOURCE_1_SIZE;
mes_set_hw_res_pkt.cleaner_shader_fence_mc_addr =
mes->resource_1_gpu_addr + hw_rsrc_size;
mes->resource_1_gpu_addr + MES11_HW_RESOURCE_1_SIZE;
return mes_v11_0_submit_pkt_and_poll_completion(mes,
&mes_set_hw_res_pkt, sizeof(mes_set_hw_res_pkt),
@@ -1431,6 +1416,21 @@ static int mes_v11_0_sw_init(struct amdgpu_ip_block *ip_block)
if (r)
return r;
if (amdgpu_sriov_is_mes_info_enable(adev) ||
adev->gfx.enable_cleaner_shader) {
r = amdgpu_bo_create_kernel(adev,
MES11_HW_RESOURCE_1_SIZE + AMDGPU_GPU_PAGE_SIZE,
PAGE_SIZE,
AMDGPU_GEM_DOMAIN_VRAM,
&adev->mes.resource_1,
&adev->mes.resource_1_gpu_addr,
&adev->mes.resource_1_addr);
if (r) {
dev_err(adev->dev, "(%d) failed to create mes resource_1 bo\n", r);
return r;
}
}
return 0;
}
@@ -1439,6 +1439,12 @@ static int mes_v11_0_sw_fini(struct amdgpu_ip_block *ip_block)
struct amdgpu_device *adev = ip_block->adev;
int pipe;
if (amdgpu_sriov_is_mes_info_enable(adev) ||
adev->gfx.enable_cleaner_shader) {
amdgpu_bo_free_kernel(&adev->mes.resource_1, &adev->mes.resource_1_gpu_addr,
&adev->mes.resource_1_addr);
}
for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) {
kfree(adev->mes.mqd_backup[pipe]);
@@ -1659,14 +1665,6 @@ static int mes_v11_0_hw_init(struct amdgpu_ip_block *ip_block)
static int mes_v11_0_hw_fini(struct amdgpu_ip_block *ip_block)
{
struct amdgpu_device *adev = ip_block->adev;
if (amdgpu_sriov_is_mes_info_enable(adev) ||
adev->gfx.enable_cleaner_shader) {
amdgpu_bo_free_kernel(&adev->mes.resource_1, &adev->mes.resource_1_gpu_addr,
&adev->mes.resource_1_addr);
}
return 0;
}