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ASoC: codecs: Add TAS67524 quad-channel audio amplifier driver
The TAS675x (TAS6754, TAS67524) are quad-channel, digital-input Class-D amplifiers with an integrated DSP, controlled over I2C. They support I2S and TDM serial audio interfaces. Signed-off-by: Sen Wang <sen@ti.com> Link: https://patch.msgid.link/20260416232640.3084132-3-sen@ti.com Signed-off-by: Mark Brown <broonie@kernel.org>
This commit is contained in:
Sen Wang
@@ -275,6 +275,7 @@ config SND_SOC_ALL_CODECS
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imply SND_SOC_TAS571X
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imply SND_SOC_TAS5720
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imply SND_SOC_TAS6424
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imply SND_SOC_TAS675X
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imply SND_SOC_TDA7419
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imply SND_SOC_TFA9879
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imply SND_SOC_TFA989X
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@@ -2237,6 +2238,17 @@ config SND_SOC_TAS6424
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Enable support for Texas Instruments TAS6424 high-efficiency
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digital input quad-channel Class-D audio power amplifiers.
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config SND_SOC_TAS675X
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tristate "Texas Instruments TAS675x Quad-Channel Audio Amplifier"
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depends on I2C
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select REGMAP_I2C
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help
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Enable support for Texas Instruments TAS675x quad-channel Class-D
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audio power amplifiers (TAS6754, TAS67524). The devices support I2S
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and TDM interfaces with real-time voltage and current sense feedback
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via SDOUT, and provide DC/AC/real-time load diagnostics for speaker
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monitoring.
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config SND_SOC_TDA7419
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tristate "ST TDA7419 audio processor"
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depends on I2C
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@@ -318,6 +318,7 @@ snd-soc-tas571x-y := tas571x.o
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snd-soc-tas5720-y := tas5720.o
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snd-soc-tas5805m-y := tas5805m.o
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snd-soc-tas6424-y := tas6424.o
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snd-soc-tas675x-y := tas675x.o
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snd-soc-tda7419-y := tda7419.o
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snd-soc-tas2770-y := tas2770.o
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snd-soc-tas2781-comlib-y := tas2781-comlib.o
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@@ -760,6 +761,7 @@ obj-$(CONFIG_SND_SOC_TAS571X) += snd-soc-tas571x.o
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obj-$(CONFIG_SND_SOC_TAS5720) += snd-soc-tas5720.o
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obj-$(CONFIG_SND_SOC_TAS5805M) += snd-soc-tas5805m.o
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obj-$(CONFIG_SND_SOC_TAS6424) += snd-soc-tas6424.o
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obj-$(CONFIG_SND_SOC_TAS675X) += snd-soc-tas675x.o
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obj-$(CONFIG_SND_SOC_TDA7419) += snd-soc-tda7419.o
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obj-$(CONFIG_SND_SOC_TAS2770) += snd-soc-tas2770.o
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obj-$(CONFIG_SND_SOC_TFA9879) += snd-soc-tfa9879.o
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2194
sound/soc/codecs/tas675x.c
Normal file
2194
sound/soc/codecs/tas675x.c
Normal file
File diff suppressed because it is too large
Load Diff
367
sound/soc/codecs/tas675x.h
Normal file
367
sound/soc/codecs/tas675x.h
Normal file
@@ -0,0 +1,367 @@
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/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* ALSA SoC Texas Instruments TAS675x Quad-Channel Audio Amplifier
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*
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* Copyright (C) 2026 Texas Instruments Incorporated - https://www.ti.com/
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* Author: Sen Wang <sen@ti.com>
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*/
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#ifndef __TAS675X_H__
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#define __TAS675X_H__
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/*
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* Book 0, Page 0 — Register Addresses
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*/
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#define TAS675X_PAGE_SIZE 256
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#define TAS675X_PAGE_REG(page, reg) ((page) * TAS675X_PAGE_SIZE + (reg))
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/* Page Control & Basic Config */
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#define TAS675X_PAGE_CTRL_REG 0x00
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#define TAS675X_RESET_REG 0x01
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#define TAS675X_OUTPUT_CTRL_REG 0x02
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#define TAS675X_STATE_CTRL_CH1_CH2_REG 0x03
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#define TAS675X_STATE_CTRL_CH3_CH4_REG 0x04
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#define TAS675X_ISENSE_CTRL_REG 0x05
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#define TAS675X_DC_DETECT_CTRL_REG 0x06
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/* Serial Audio Port */
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#define TAS675X_SCLK_INV_CTRL_REG 0x20
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#define TAS675X_AUDIO_IF_CTRL_REG 0x21
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#define TAS675X_SDIN_CTRL_REG 0x23
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#define TAS675X_SDOUT_CTRL_REG 0x25
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#define TAS675X_SDIN_OFFSET_MSB_REG 0x27
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#define TAS675X_SDIN_AUDIO_OFFSET_REG 0x28
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#define TAS675X_SDIN_LL_OFFSET_REG 0x29
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#define TAS675X_SDIN_CH_SWAP_REG 0x2A
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#define TAS675X_SDOUT_OFFSET_MSB_REG 0x2C
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#define TAS675X_VPREDICT_OFFSET_REG 0x2D
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#define TAS675X_ISENSE_OFFSET_REG 0x2E
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#define TAS675X_SDOUT_EN_REG 0x31
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#define TAS675X_LL_EN_REG 0x32
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/* DSP & Core Audio Control */
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#define TAS675X_RTLDG_EN_REG 0x37
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#define TAS675X_DC_BLOCK_BYP_REG 0x39
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#define TAS675X_DSP_CTRL_REG 0x3A
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#define TAS675X_PAGE_AUTO_INC_REG 0x3B
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/* Volume & Mute */
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#define TAS675X_DIG_VOL_CH1_REG 0x40
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#define TAS675X_DIG_VOL_CH2_REG 0x41
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#define TAS675X_DIG_VOL_CH3_REG 0x42
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#define TAS675X_DIG_VOL_CH4_REG 0x43
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#define TAS675X_DIG_VOL_RAMP_CTRL_REG 0x44
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#define TAS675X_DIG_VOL_COMBINE_CTRL_REG 0x46
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#define TAS675X_AUTO_MUTE_EN_REG 0x47
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#define TAS675X_AUTO_MUTE_TIMING_CH1_CH2_REG 0x48
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#define TAS675X_AUTO_MUTE_TIMING_CH3_CH4_REG 0x49
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/* Analog Gain & Power Stage */
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#define TAS675X_ANALOG_GAIN_CH1_CH2_REG 0x4A
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#define TAS675X_ANALOG_GAIN_CH3_CH4_REG 0x4B
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#define TAS675X_ANALOG_GAIN_RAMP_CTRL_REG 0x4E
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#define TAS675X_PULSE_INJECTION_EN_REG 0x52
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#define TAS675X_CBC_CTRL_REG 0x54
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#define TAS675X_CURRENT_LIMIT_CTRL_REG 0x55
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#define TAS675X_DAC_CLK_REG 0x5A
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#define TAS675X_ISENSE_CAL_REG 0x5B
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/* Spread Spectrum & PWM Phase */
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#define TAS675X_PWM_PHASE_CTRL_REG 0x60
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#define TAS675X_SS_CTRL_REG 0x61
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#define TAS675X_SS_RANGE_CTRL_REG 0x62
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#define TAS675X_SS_DWELL_CTRL_REG 0x66
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#define TAS675X_RAMP_PHASE_CTRL_GPO_REG 0x68
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#define TAS675X_PWM_PHASE_M_CTRL_CH1_REG 0x69
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#define TAS675X_PWM_PHASE_M_CTRL_CH2_REG 0x6A
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#define TAS675X_PWM_PHASE_M_CTRL_CH3_REG 0x6B
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#define TAS675X_PWM_PHASE_M_CTRL_CH4_REG 0x6C
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/* Status & Reporting */
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#define TAS675X_AUTO_MUTE_STATUS_REG 0x71
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#define TAS675X_STATE_REPORT_CH1_CH2_REG 0x72
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#define TAS675X_STATE_REPORT_CH3_CH4_REG 0x73
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#define TAS675X_PVDD_SENSE_REG 0x74
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#define TAS675X_TEMP_GLOBAL_REG 0x75
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#define TAS675X_FS_MON_REG 0x76
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#define TAS675X_SCLK_MON_REG 0x77
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#define TAS675X_REPORT_ROUTING_1_REG 0x7C
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/* Memory Paging & Book Control */
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#define TAS675X_SETUP_REG1 0x7D
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#define TAS675X_SETUP_REG2 0x7E
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#define TAS675X_BOOK_CTRL_REG 0x7F
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/* Fault Status */
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#define TAS675X_POWER_FAULT_STATUS_1_REG 0x7D
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#define TAS675X_POWER_FAULT_STATUS_2_REG 0x80
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#define TAS675X_OT_FAULT_REG 0x81
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#define TAS675X_OTW_STATUS_REG 0x82
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#define TAS675X_CLIP_WARN_STATUS_REG 0x83
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#define TAS675X_CBC_WARNING_STATUS_REG 0x85
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/* Latched Fault Registers */
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#define TAS675X_POWER_FAULT_LATCHED_REG 0x86
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#define TAS675X_OTSD_LATCHED_REG 0x87
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#define TAS675X_OTW_LATCHED_REG 0x88
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#define TAS675X_CLIP_WARN_LATCHED_REG 0x89
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#define TAS675X_CLK_FAULT_LATCHED_REG 0x8A
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#define TAS675X_RTLDG_OL_SL_FAULT_LATCHED_REG 0x8B
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#define TAS675X_CBC_FAULT_WARN_LATCHED_REG 0x8D
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#define TAS675X_OC_DC_FAULT_LATCHED_REG 0x8E
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#define TAS675X_OTSD_RECOVERY_EN_REG 0x8F
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/* Protection & Routing Controls */
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#define TAS675X_REPORT_ROUTING_2_REG 0x90
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#define TAS675X_REPORT_ROUTING_3_REG 0x91
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#define TAS675X_REPORT_ROUTING_4_REG 0x92
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#define TAS675X_CLIP_DETECT_CTRL_REG 0x93
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#define TAS675X_REPORT_ROUTING_5_REG 0x94
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/* GPIO Pin Configuration */
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#define TAS675X_GPIO1_OUTPUT_SEL_REG 0x95
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#define TAS675X_GPIO2_OUTPUT_SEL_REG 0x96
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#define TAS675X_GPIO_INPUT_SLEEP_HIZ_REG 0x9B
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#define TAS675X_GPIO_INPUT_PLAY_SLEEP_REG 0x9C
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#define TAS675X_GPIO_INPUT_MUTE_REG 0x9D
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#define TAS675X_GPIO_INPUT_SYNC_REG 0x9E
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#define TAS675X_GPIO_INPUT_SDIN2_REG 0x9F
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#define TAS675X_GPIO_CTRL_REG 0xA0
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#define TAS675X_GPIO_INVERT_REG 0xA1
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/* Load Diagnostics Config */
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#define TAS675X_DC_LDG_CTRL_REG 0xB0
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#define TAS675X_DC_LDG_LO_CTRL_REG 0xB1
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#define TAS675X_DC_LDG_TIME_CTRL_REG 0xB2
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#define TAS675X_DC_LDG_SL_CH1_CH2_CTRL_REG 0xB3
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#define TAS675X_DC_LDG_SL_CH3_CH4_CTRL_REG 0xB4
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#define TAS675X_AC_LDG_CTRL_REG 0xB5
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#define TAS675X_TWEETER_DETECT_CTRL_REG 0xB6
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#define TAS675X_TWEETER_DETECT_THRESH_REG 0xB7
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#define TAS675X_AC_LDG_FREQ_CTRL_REG 0xB8
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#define TAS675X_TEMP_CH1_CH2_REG 0xBB
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#define TAS675X_TEMP_CH3_CH4_REG 0xBC
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#define TAS675X_WARN_OT_MAX_FLAG_REG 0xBD
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/* DC Load Diagnostic Reports */
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#define TAS675X_DC_LDG_REPORT_CH1_CH2_REG 0xC0
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#define TAS675X_DC_LDG_REPORT_CH3_CH4_REG 0xC1
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#define TAS675X_DC_LDG_RESULT_REG 0xC2
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#define TAS675X_AC_LDG_REPORT_CH1_R_REG 0xC3
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#define TAS675X_AC_LDG_REPORT_CH1_I_REG 0xC4
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#define TAS675X_AC_LDG_REPORT_CH2_R_REG 0xC5
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#define TAS675X_AC_LDG_REPORT_CH2_I_REG 0xC6
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#define TAS675X_AC_LDG_REPORT_CH3_R_REG 0xC7
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#define TAS675X_AC_LDG_REPORT_CH3_I_REG 0xC8
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#define TAS675X_AC_LDG_REPORT_CH4_R_REG 0xC9
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#define TAS675X_AC_LDG_REPORT_CH4_I_REG 0xCA
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#define TAS675X_TWEETER_REPORT_REG 0xCB
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/* RTLDG Impedance */
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#define TAS675X_CH1_RTLDG_IMP_MSB_REG 0xD1
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#define TAS675X_CH1_RTLDG_IMP_LSB_REG 0xD2
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#define TAS675X_CH2_RTLDG_IMP_MSB_REG 0xD3
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#define TAS675X_CH2_RTLDG_IMP_LSB_REG 0xD4
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#define TAS675X_CH3_RTLDG_IMP_MSB_REG 0xD5
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#define TAS675X_CH3_RTLDG_IMP_LSB_REG 0xD6
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#define TAS675X_CH4_RTLDG_IMP_MSB_REG 0xD7
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#define TAS675X_CH4_RTLDG_IMP_LSB_REG 0xD8
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/* DC Load Diagnostic Resistance */
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#define TAS675X_DC_LDG_DCR_MSB_REG 0xD9
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#define TAS675X_CH1_DC_LDG_DCR_LSB_REG 0xDA
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#define TAS675X_CH2_DC_LDG_DCR_LSB_REG 0xDB
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#define TAS675X_CH3_DC_LDG_DCR_LSB_REG 0xDC
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#define TAS675X_CH4_DC_LDG_DCR_LSB_REG 0xDD
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/* Over-Temperature Warning */
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#define TAS675X_OTW_CTRL_CH1_CH2_REG 0xE2
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#define TAS675X_OTW_CTRL_CH3_CH4_REG 0xE3
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/* RESET_REG (all bits auto-clear) */
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#define TAS675X_DEVICE_RESET BIT(4)
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#define TAS675X_FAULT_CLEAR BIT(3)
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#define TAS675X_REGISTER_RESET BIT(0)
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/* STATE_CTRL and STATE_REPORT — Channel state values */
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#define TAS675X_STATE_DEEPSLEEP 0x00
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#define TAS675X_STATE_LOAD_DIAG 0x01
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#define TAS675X_STATE_SLEEP 0x02
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#define TAS675X_STATE_HIZ 0x03
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#define TAS675X_STATE_PLAY 0x04
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/* Additional STATE_REPORT values */
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#define TAS675X_STATE_FAULT 0x05
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#define TAS675X_STATE_AUTOREC 0x06
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/* Combined values for both channel pairs in one register */
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#define TAS675X_STATE_DEEPSLEEP_BOTH \
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(TAS675X_STATE_DEEPSLEEP | (TAS675X_STATE_DEEPSLEEP << 4))
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#define TAS675X_STATE_LOAD_DIAG_BOTH \
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(TAS675X_STATE_LOAD_DIAG | (TAS675X_STATE_LOAD_DIAG << 4))
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#define TAS675X_STATE_SLEEP_BOTH \
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(TAS675X_STATE_SLEEP | (TAS675X_STATE_SLEEP << 4))
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#define TAS675X_STATE_HIZ_BOTH \
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(TAS675X_STATE_HIZ | (TAS675X_STATE_HIZ << 4))
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#define TAS675X_STATE_PLAY_BOTH \
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(TAS675X_STATE_PLAY | (TAS675X_STATE_PLAY << 4))
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#define TAS675X_STATE_FAULT_BOTH \
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(TAS675X_STATE_FAULT | (TAS675X_STATE_FAULT << 4))
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/* STATE_CTRL_CH1_CH2 / STATE_CTRL_CH3_CH4 — mute bits */
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#define TAS675X_CH1_MUTE_BIT BIT(7)
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#define TAS675X_CH2_MUTE_BIT BIT(3)
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#define TAS675X_CH_MUTE_BOTH (TAS675X_CH1_MUTE_BIT | TAS675X_CH2_MUTE_BIT)
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/* SCLK_INV_CTRL_REG */
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#define TAS675X_SCLK_INV_TX_BIT BIT(5)
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#define TAS675X_SCLK_INV_RX_BIT BIT(4)
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#define TAS675X_SCLK_INV_MASK (TAS675X_SCLK_INV_TX_BIT | TAS675X_SCLK_INV_RX_BIT)
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/* AUDIO_IF_CTRL_REG */
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#define TAS675X_TDM_EN_BIT BIT(4)
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#define TAS675X_SAP_FMT_MASK GENMASK(3, 2)
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#define TAS675X_SAP_FMT_I2S (0x00 << 2)
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#define TAS675X_SAP_FMT_TDM (0x01 << 2)
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#define TAS675X_SAP_FMT_RIGHT_J (0x02 << 2)
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#define TAS675X_SAP_FMT_LEFT_J (0x03 << 2)
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#define TAS675X_FS_PULSE_MASK GENMASK(1, 0)
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#define TAS675X_FS_PULSE_SHORT 0x01
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/* SDIN_CTRL_REG */
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#define TAS675X_SDIN_AUDIO_WL_MASK GENMASK(3, 2)
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#define TAS675X_SDIN_LL_WL_MASK GENMASK(1, 0)
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#define TAS675X_SDIN_WL_MASK (TAS675X_SDIN_AUDIO_WL_MASK | TAS675X_SDIN_LL_WL_MASK)
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/* SDOUT_CTRL_REG */
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#define TAS675X_SDOUT_SELECT_MASK GENMASK(7, 4)
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#define TAS675X_SDOUT_SELECT_TDM_SDOUT1 0x00
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#define TAS675X_SDOUT_SELECT_NON_TDM 0x10
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#define TAS675X_SDOUT_VP_WL_MASK GENMASK(3, 2)
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#define TAS675X_SDOUT_IS_WL_MASK GENMASK(1, 0)
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#define TAS675X_SDOUT_WL_MASK (TAS675X_SDOUT_VP_WL_MASK | TAS675X_SDOUT_IS_WL_MASK)
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/* SDOUT_EN_REG */
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#define TAS675X_SDOUT_NON_TDM_SEL_MASK GENMASK(5, 4)
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#define TAS675X_SDOUT_NON_TDM_SEL_VPREDICT (0x0 << 4)
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#define TAS675X_SDOUT_NON_TDM_SEL_ISENSE (0x1 << 4)
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#define TAS675X_SDOUT_EN_VPREDICT BIT(0)
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#define TAS675X_SDOUT_EN_ISENSE BIT(1)
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#define TAS675X_SDOUT_EN_NON_TDM_ALL GENMASK(1, 0)
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/* Word length values (shared by SDIN_CTRL and SDOUT_CTRL) */
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#define TAS675X_WL_16BIT 0x00
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#define TAS675X_WL_20BIT 0x01
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#define TAS675X_WL_24BIT 0x02
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#define TAS675X_WL_32BIT 0x03
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/* SDIN_OFFSET_MSB_REG */
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#define TAS675X_SDIN_AUDIO_OFF_MSB_MASK GENMASK(7, 6)
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#define TAS675X_SDIN_LL_OFF_MSB_MASK GENMASK(5, 4)
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/* SDOUT_OFFSET_MSB_REG */
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#define TAS675X_SDOUT_VP_OFF_MSB_MASK GENMASK(7, 6)
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#define TAS675X_SDOUT_IS_OFF_MSB_MASK GENMASK(5, 4)
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/* RTLDG_EN_REG */
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#define TAS675X_RTLDG_CLIP_MASK_BIT BIT(4)
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#define TAS675X_RTLDG_CH_EN_MASK GENMASK(3, 0)
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/* DC_LDG_CTRL_REG */
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#define TAS675X_LDG_ABORT_BIT BIT(7)
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#define TAS675X_LDG_BUFFER_WAIT_MASK GENMASK(6, 5)
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#define TAS675X_LDG_WAIT_BYPASS_BIT BIT(2)
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#define TAS675X_SLOL_DISABLE_BIT BIT(1)
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#define TAS675X_LDG_BYPASS_BIT BIT(0)
|
||||
|
||||
/* DC_LDG_TIME_CTRL_REG */
|
||||
#define TAS675X_LDG_RAMP_SLOL_MASK GENMASK(7, 6)
|
||||
#define TAS675X_LDG_SETTLING_SLOL_MASK GENMASK(5, 4)
|
||||
#define TAS675X_LDG_RAMP_S2PG_MASK GENMASK(3, 2)
|
||||
#define TAS675X_LDG_SETTLING_S2PG_MASK GENMASK(1, 0)
|
||||
|
||||
/* AC_LDG_CTRL_REG */
|
||||
#define TAS675X_AC_DIAG_GAIN_BIT BIT(4)
|
||||
#define TAS675X_AC_DIAG_START_MASK GENMASK(3, 0)
|
||||
|
||||
/* DC_LDG_RESULT_REG */
|
||||
#define TAS675X_DC_LDG_LO_RESULT_MASK GENMASK(7, 4)
|
||||
#define TAS675X_DC_LDG_PASS_MASK GENMASK(3, 0)
|
||||
|
||||
/* Load Diagnostics Timing Constants */
|
||||
#define TAS675X_POLL_INTERVAL_US 10000
|
||||
#define TAS675X_STATE_TRANSITION_TIMEOUT_US 50000
|
||||
#define TAS675X_DC_LDG_TIMEOUT_US 300000
|
||||
#define TAS675X_AC_LDG_TIMEOUT_US 400000
|
||||
|
||||
/* GPIO_CTRL_REG */
|
||||
#define TAS675X_GPIO1_OUTPUT_EN BIT(7)
|
||||
#define TAS675X_GPIO2_OUTPUT_EN BIT(6)
|
||||
#define TAS675X_GPIO_CTRL_RSTVAL 0x22
|
||||
|
||||
/* GPIO output select values */
|
||||
#define TAS675X_GPIO_SEL_LOW 0x00
|
||||
#define TAS675X_GPIO_SEL_AUTO_MUTE_ALL 0x02
|
||||
#define TAS675X_GPIO_SEL_AUTO_MUTE_CH4 0x03
|
||||
#define TAS675X_GPIO_SEL_AUTO_MUTE_CH3 0x04
|
||||
#define TAS675X_GPIO_SEL_AUTO_MUTE_CH2 0x05
|
||||
#define TAS675X_GPIO_SEL_AUTO_MUTE_CH1 0x06
|
||||
#define TAS675X_GPIO_SEL_SDOUT2 0x08
|
||||
#define TAS675X_GPIO_SEL_SDOUT1 0x09
|
||||
#define TAS675X_GPIO_SEL_WARN 0x0A
|
||||
#define TAS675X_GPIO_SEL_FAULT 0x0B
|
||||
#define TAS675X_GPIO_SEL_CLOCK_SYNC 0x0E
|
||||
#define TAS675X_GPIO_SEL_INVALID_CLK 0x0F
|
||||
#define TAS675X_GPIO_SEL_HIGH 0x13
|
||||
|
||||
/* GPIO input function encoding (flag bit | function ID) */
|
||||
#define TAS675X_GPIO_FUNC_INPUT 0x100
|
||||
|
||||
/* Input Function IDs */
|
||||
#define TAS675X_GPIO_IN_ID_MUTE 0
|
||||
#define TAS675X_GPIO_IN_ID_PHASE_SYNC 1
|
||||
#define TAS675X_GPIO_IN_ID_SDIN2 2
|
||||
#define TAS675X_GPIO_IN_ID_DEEP_SLEEP 3
|
||||
#define TAS675X_GPIO_IN_ID_HIZ 4
|
||||
#define TAS675X_GPIO_IN_ID_PLAY 5
|
||||
#define TAS675X_GPIO_IN_ID_SLEEP 6
|
||||
#define TAS675X_GPIO_IN_NUM 7
|
||||
|
||||
#define TAS675X_GPIO_IN_MUTE (TAS675X_GPIO_FUNC_INPUT | TAS675X_GPIO_IN_ID_MUTE)
|
||||
#define TAS675X_GPIO_IN_PHASE_SYNC \
|
||||
(TAS675X_GPIO_FUNC_INPUT | TAS675X_GPIO_IN_ID_PHASE_SYNC)
|
||||
#define TAS675X_GPIO_IN_SDIN2 (TAS675X_GPIO_FUNC_INPUT | TAS675X_GPIO_IN_ID_SDIN2)
|
||||
#define TAS675X_GPIO_IN_DEEP_SLEEP \
|
||||
(TAS675X_GPIO_FUNC_INPUT | TAS675X_GPIO_IN_ID_DEEP_SLEEP)
|
||||
#define TAS675X_GPIO_IN_HIZ (TAS675X_GPIO_FUNC_INPUT | TAS675X_GPIO_IN_ID_HIZ)
|
||||
#define TAS675X_GPIO_IN_PLAY (TAS675X_GPIO_FUNC_INPUT | TAS675X_GPIO_IN_ID_PLAY)
|
||||
#define TAS675X_GPIO_IN_SLEEP (TAS675X_GPIO_FUNC_INPUT | TAS675X_GPIO_IN_ID_SLEEP)
|
||||
|
||||
/* GPIO input 3-bit mux field masks */
|
||||
#define TAS675X_GPIO_IN_MUTE_MASK GENMASK(2, 0)
|
||||
#define TAS675X_GPIO_IN_SYNC_MASK GENMASK(2, 0)
|
||||
#define TAS675X_GPIO_IN_SDIN2_MASK GENMASK(6, 4)
|
||||
#define TAS675X_GPIO_IN_DEEP_SLEEP_MASK GENMASK(6, 4)
|
||||
#define TAS675X_GPIO_IN_HIZ_MASK GENMASK(2, 0)
|
||||
#define TAS675X_GPIO_IN_PLAY_MASK GENMASK(6, 4)
|
||||
#define TAS675X_GPIO_IN_SLEEP_MASK GENMASK(2, 0)
|
||||
|
||||
/* Book addresses for tas675x_select_book() */
|
||||
#define TAS675X_BOOK_DEFAULT 0x00
|
||||
#define TAS675X_BOOK_DSP 0x8C
|
||||
|
||||
/* DSP memory addresses (DSP Book) */
|
||||
#define TAS675X_DSP_PAGE_RTLDG 0x22
|
||||
#define TAS675X_DSP_RTLDG_OL_THRESH_REG 0x98
|
||||
#define TAS675X_DSP_RTLDG_SL_THRESH_REG 0x9C
|
||||
|
||||
#define TAS675X_DSP_PARAM_ID_OL_THRESH 0
|
||||
#define TAS675X_DSP_PARAM_ID_SL_THRESH 1
|
||||
|
||||
/* Setup Mode Entry/Exit*/
|
||||
#define TAS675X_SETUP_ENTER_VAL1 0x11
|
||||
#define TAS675X_SETUP_ENTER_VAL2 0xFF
|
||||
#define TAS675X_SETUP_EXIT_VAL 0x00
|
||||
|
||||
#endif /* __TAS675X_H__ */
|
||||
Reference in New Issue
Block a user