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ARM: dts: arria10: update NAND clocking

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The NAND IP needs 3 clocks(nand_x_clk, nand_clk, and nand_ecc_clk). This
patch adds a nand_clk, which is derived from the nand_x_clk, but has a
fixed divider of 4, and the nand_ecc_clk, which is derived from the
nand_x_clk.

Update the NAND node to use the additional clocks.

Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
---
v2: add nand_ecc_clk and update commit message
This commit is contained in:
Dinh Nguyen
2018-07-09 13:47:20 -05:00
parent 9a8e3cfd34
commit 12b2982a1f
1 changed files with 18 additions and 2 deletions
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20
arch/arm/boot/dts/socfpga_arria10.dtsi
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@@ -377,13 +377,28 @@ qspi_clk: qspi_clk {
clk-gate = <0xC8 11>;
};
nand_clk: nand_clk {
nand_x_clk: nand_x_clk {
#clock-cells = <0>;
compatible = "altr,socfpga-a10-gate-clk";
clocks = <&l4_mp_clk>;
clk-gate = <0xC8 10>;
};
nand_ecc_clk: nand_ecc_clk {
#clock-cells = <0>;
compatible = "altr,socfpga-a10-gate-clk";
clocks = <&nand_x_clk>;
clk-gate = <0xC8 10>;
};
nand_clk: nand_clk {
#clock-cells = <0>;
compatible = "altr,socfpga-a10-gate-clk";
clocks = <&nand_x_clk>;
fixed-divider = <4>;
clk-gate = <0xC8 10>;
};
spi_m_clk: spi_m_clk {
#clock-cells = <0>;
compatible = "altr,socfpga-a10-gate-clk";
@@ -650,7 +665,8 @@ nand: nand@ffb90000 {
reg-names = "nand_data", "denali_reg";
interrupts = <0 99 4>;
dma-mask = <0xffffffff>;
clocks = <&nand_clk>;
clocks = <&nand_clk>, <&nand_x_clk>, <&nand_ecc_clk>;
clock-names = "nand", "nand_x", "ecc";
status = "disabled";
};