arm64: arch_timer: reuse arch_timer_read_cnt{p,v}ct_el0() helpers

__arch_counter_get_cntpct() and __arch_counter_get_cntvct() open-code
the same ECV-aware ALTERNATIVE block that arch_timer_read_cntpct_el0()
and arch_timer_read_cntvct_el0() already provide in the same header.
The two pairs are byte-for-byte identical except for the trailing
arch_counter_enforce_ordering() the __arch_counter_get_* variants add.

Replace the duplicated inline assembly in __arch_counter_get_cntpct()
and __arch_counter_get_cntvct() with calls to the corresponding helpers.
This mirrors commit 00b39d1509 ("arm64: vdso: Use
__arch_counter_get_cntvct()"), which removed similar duplication from
the vDSO, and keeps the system-counter read sequence in a single place,
reducing assembly code in the kernell

No functional change: the resulting inline assembly, alternatives, and
clobbers are unchanged; only the source-level expression of the read
moves into the existing helper.

Verified by rebuilding the consumers of these helpers before and after
the change and comparing the resulting disassembly:

  - arch/arm64/kernel/vdso/vdso.so (final linked vDSO):
      bit-identical (same sha256 across rebuilds)
  - arch/arm64/kernel/vdso/vgettimeofday.o:    identical disassembly
  - arch/arm64/lib/delay.o:                    identical disassembly
  - drivers/clocksource/arm_arch_timer.o:      same 50 functions with
      byte-identical instruction streams; only difference is function
      ordering inside .text and NOP padding, with no opcodes added or
      removed.

Signed-off-by: Breno Leitao <leitao@debian.org>
Signed-off-by: Will Deacon <will@kernel.org>
This commit is contained in:
Breno Leitao
2026-05-23 12:59:26 -04:00
committed by Will Deacon
parent 6c2ccb4979
commit 11c33ffb3a

View File

@@ -178,12 +178,8 @@ static __always_inline u64 __arch_counter_get_cntpct_stable(void)
static __always_inline u64 __arch_counter_get_cntpct(void)
{
u64 cnt;
u64 cnt = arch_timer_read_cntpct_el0();
asm volatile(ALTERNATIVE("isb\n mrs %0, cntpct_el0",
"nop\n" __mrs_s("%0", SYS_CNTPCTSS_EL0),
ARM64_HAS_ECV)
: "=r" (cnt));
arch_counter_enforce_ordering(cnt);
return cnt;
}
@@ -199,12 +195,8 @@ static __always_inline u64 __arch_counter_get_cntvct_stable(void)
static __always_inline u64 __arch_counter_get_cntvct(void)
{
u64 cnt;
u64 cnt = arch_timer_read_cntvct_el0();
asm volatile(ALTERNATIVE("isb\n mrs %0, cntvct_el0",
"nop\n" __mrs_s("%0", SYS_CNTVCTSS_EL0),
ARM64_HAS_ECV)
: "=r" (cnt));
arch_counter_enforce_ordering(cnt);
return cnt;
}