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arm64: zynqmp: Setup clock for DP and DPDMA

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Clocks are coming from shared HW design where these frequencies should be
aligned with PLL setup.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/807e22371394222f728ff7d6b190a96a12145439.1683034376.git.michal.simek@amd.com
This commit is contained in:
Michal Simek
2023-05-02 15:35:46 +02:00
parent fc57b6c929
commit 116de80ada
3 changed files with 8 additions and 0 deletions
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4
arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi
View File

@@ -248,10 +248,14 @@ &xilinx_ams {
&zynqmp_dpdma {
clocks = <&zynqmp_clk DPDMA_REF>;
assigned-clocks = <&zynqmp_clk DPDMA_REF>; /* apll */
};
&zynqmp_dpsub {
clocks = <&zynqmp_clk TOPSW_LSBUS>,
<&zynqmp_clk DP_AUDIO_REF>,
<&zynqmp_clk DP_VIDEO_REF>;
assigned-clocks = <&zynqmp_clk DP_STC_REF>,
<&zynqmp_clk DP_AUDIO_REF>,
<&zynqmp_clk DP_VIDEO_REF>; /* rpll, rpll, vpll */
};

2
arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revA.dtso
View File

@@ -98,10 +98,12 @@ &zynqmp_dpsub {
status = "disabled";
phy-names = "dp-phy0", "dp-phy1";
phys = <&psgtr 1 PHY_TYPE_DP 0 0>, <&psgtr 0 PHY_TYPE_DP 1 0>;
assigned-clock-rates = <27000000>, <25000000>, <300000000>;
};
&zynqmp_dpdma {
status = "okay";
assigned-clock-rates = <600000000>;
};
&usb0 {

2
arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revB.dtso
View File

@@ -79,10 +79,12 @@ &zynqmp_dpsub {
status = "disabled";
phy-names = "dp-phy0", "dp-phy1";
phys = <&psgtr 1 PHY_TYPE_DP 0 0>, <&psgtr 0 PHY_TYPE_DP 1 0>;
assigned-clock-rates = <27000000>, <25000000>, <300000000>;
};
&zynqmp_dpdma {
status = "okay";
assigned-clock-rates = <600000000>;
};
&usb0 {