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ARM: dts: socfpga: fix register entry for timer3 on Arria10

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Fixes the register address for the timer3 entry on Arria10.

Fixes: 475dc86d08 ("arm: dts: socfpga: Add a base DTSI for Altera's Arria10 SOC")
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
This commit is contained in:
Dinh Nguyen
2020-07-31 10:26:40 -05:00
parent 9123e3a74e
commit 0ff5a4812b
1 changed files with 1 additions and 1 deletions
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2
arch/arm/boot/dts/socfpga_arria10.dtsi
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@@ -821,7 +821,7 @@ timer2: timer2@ffd00000 {
timer3: timer3@ffd00100 {
compatible = "snps,dw-apb-timer";
interrupts = <0 118 IRQ_TYPE_LEVEL_HIGH>;
reg = <0xffd01000 0x100>;
reg = <0xffd00100 0x100>;
clocks = <&l4_sys_free_clk>;
clock-names = "timer";
resets = <&rst L4SYSTIMER1_RESET>;