mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
synced 2026-08-31 10:31:33 -04:00
Merge tag 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/rmk/linux
Pull arm updates from Russell King:
"Updates for 7.3:
- add module description for kprobes testing module
- remove references to CONFIG_CPU_ARM92x_CPU_IDLE options
- expand comment in ARM's __switch_to()
Also a number of fixes that missed 7.2:
- disable broken eBPF on RiscPC
- more BKPT fixes (guys, it's a *very* bad idea when everyone uses
the BKPT instruction for their own differing purposes)
- another preempt-rt fix, this time for siglock / CPU timers
- fix another path where we try to send signals to processes with
interrupts disabled
- acquire mmap write lock for show_pte() with user faults"
* tag 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/rmk/linux:
ARM: 9480/1: entry: expand comment in __switch_to
ARM: 9478/1: Remove references to removed CONFIG_CPU_ARM92x_CPU_IDLE options
ARM: 9485/1: mm: acquire mmap write lock around show_pte() for user faults
ARM: 9484/1: enable interrupts when unhandled user faults are triggered
ARM: 9483/1: select HAVE_POSIX_CPU_TIMERS_TASK_WORK
ARM: 9481/2: breakpoint: CFI breakpoints only on demand
ARM: 9477/1: Disable broken eBPF JIT on the Risc PC
ARM: 9473/1: kprobes: test: add MODULE_DESCRIPTION
This commit is contained in:
@@ -99,7 +99,7 @@ config ARM
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select HAVE_ARCH_TRACEHOOK
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select HAVE_ARCH_TRANSPARENT_HUGEPAGE if ARM_LPAE
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select HAVE_ARM_SMCCC if CPU_V7
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select HAVE_EBPF_JIT if !CPU_ENDIAN_BE32
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select HAVE_EBPF_JIT if !CPU_ENDIAN_BE32 && !CPU_32v3
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select HAVE_CONTEXT_TRACKING_USER
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select HAVE_C_RECORDMCOUNT
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select HAVE_BUILDTIME_MCOUNT_SORT
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@@ -134,6 +134,7 @@ config ARM
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select HAVE_PERF_EVENTS
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select HAVE_PERF_REGS
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select HAVE_PERF_USER_STACK_DUMP
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select HAVE_POSIX_CPU_TIMERS_TASK_WORK
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select MMU_GATHER_RCU_TABLE_FREE if SMP && ARM_LPAE
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select HAVE_REGS_AND_STACK_ACCESS_API
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select HAVE_RSEQ
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@@ -557,9 +557,16 @@ ENTRY(__switch_to)
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ldmia r4, {r4 - sl, fp, ip, lr} @ Load all regs saved previously
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#ifdef CONFIG_VMAP_STACK
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@
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@ Do a dummy read from the new stack while running from the old one so
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@ that we can rely on do_translation_fault() to fix up any stale PMD
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@ entries covering the vmalloc region.
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@ For a non-lazy mm switch, check_vmalloc_seq() has ensured that
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@ that the active mm's page tables have mappings for the prev
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@ task's stack and the next task's stack.
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@
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@ For a lazy mm switch the active mm's page tables have mappings
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@ for the prev task's stack but might not have mappings for the
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@ new task's stack. Do a dummy read from the new stack while
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@ running from the old stack so that we can rely on
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@ do_translation_fault() to populate missing PMD entries covering the
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@ new task's stack in the old task's page tables.
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@
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ldr r2, [ip]
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#ifdef CONFIG_KASAN_VMALLOC
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@@ -929,10 +929,6 @@ static void hw_breakpoint_cfi_handler(struct pt_regs *regs)
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break;
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}
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}
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#else
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static void hw_breakpoint_cfi_handler(struct pt_regs *regs)
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{
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}
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#endif
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/*
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@@ -964,9 +960,14 @@ static int hw_breakpoint_pending(unsigned long addr, unsigned int fsr,
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case ARM_ENTRY_SYNC_WATCHPOINT:
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watchpoint_handler(addr, fsr, regs);
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break;
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#ifdef CONFIG_CFI
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case ARM_ENTRY_CFI_BREAKPOINT:
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hw_breakpoint_cfi_handler(regs);
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if (user_mode(regs))
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ret = 1; /* Don't handle userspace BKPT */
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else
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hw_breakpoint_cfi_handler(regs);
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break;
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#endif
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default:
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ret = 1; /* Unhandled fault. */
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}
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@@ -181,7 +181,11 @@ __do_user_fault(unsigned long addr, unsigned int fsr, unsigned int sig,
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pr_err("8<--- cut here ---\n");
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pr_err("%s: unhandled page fault (%d) at 0x%08lx, code 0x%03x\n",
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tsk->comm, sig, addr, fsr);
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show_pte(KERN_ERR, tsk->mm, addr);
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if (likely(addr < TASK_SIZE)) {
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mmap_write_lock(tsk->mm);
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show_pte(KERN_ERR, tsk->mm, addr);
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mmap_write_unlock(tsk->mm);
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}
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show_regs(regs);
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}
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#endif
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@@ -633,10 +637,21 @@ do_DataAbort(unsigned long addr, unsigned int fsr, struct pt_regs *regs)
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if (!inf->fn(addr, fsr & ~FSR_LNX_PF, regs))
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return;
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if (likely(user_mode(regs)))
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local_irq_enable();
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pr_alert("8<--- cut here ---\n");
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pr_alert("Unhandled fault: %s (0x%03x) at 0x%08lx\n",
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inf->name, fsr, addr);
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show_pte(KERN_ALERT, current->mm, addr);
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if (likely(user_mode(regs))) {
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if (addr < TASK_SIZE) {
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mmap_write_lock(current->mm);
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show_pte(KERN_ALERT, current->mm, addr);
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mmap_write_unlock(current->mm);
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}
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} else {
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show_pte(KERN_ALERT, current->mm, addr);
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}
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arm_notify_die("", regs, inf->sig, inf->code, (void __user *)addr,
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fsr, 0);
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@@ -663,6 +678,9 @@ do_PrefetchAbort(unsigned long addr, unsigned int ifsr, struct pt_regs *regs)
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if (!inf->fn(addr, ifsr | FSR_LNX_PF, regs))
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return;
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if (likely(user_mode(regs)))
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local_irq_enable();
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pr_alert("8<--- cut here ---\n");
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pr_alert("Unhandled prefetch abort: %s (0x%03x) at 0x%08lx\n",
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inf->name, ifsr, addr);
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@@ -8,8 +8,6 @@
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*
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* These are the low level assembler for performing cache and TLB
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* functions on the arm920.
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*
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* CONFIG_CPU_ARM920_CPU_IDLE -> nohlt
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*/
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#include <linux/linkage.h>
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#include <linux/init.h>
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@@ -9,8 +9,6 @@
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*
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* These are the low level assembler for performing cache and TLB
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* functions on the arm922.
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*
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* CONFIG_CPU_ARM922_CPU_IDLE -> nohlt
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*/
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#include <linux/linkage.h>
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#include <linux/init.h>
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@@ -15,8 +15,6 @@
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* These are the low level assembler for performing cache and TLB
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* functions on the arm925.
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*
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* CONFIG_CPU_ARM925_CPU_IDLE -> nohlt
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*
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* Some additional notes based on deciphering the TI TRM on OMAP-5910:
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*
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* NOTE1: The TI925T Configuration Register bit "D-cache clean and flush
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@@ -8,8 +8,6 @@
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*
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* These are the low level assembler for performing cache and TLB
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* functions on the arm926.
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*
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* CONFIG_CPU_ARM926_CPU_IDLE -> nohlt
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*/
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#include <linux/linkage.h>
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#include <linux/init.h>
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@@ -1649,24 +1649,16 @@ static int __init run_all_tests(void)
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return ret;
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}
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late_initcall(run_all_tests);
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/*
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* Module setup
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*/
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#ifdef MODULE
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static void __exit kprobe_test_exit(void)
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{
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}
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module_init(run_all_tests)
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module_exit(kprobe_test_exit)
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MODULE_DESCRIPTION("Test code for ARM kprobes");
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MODULE_LICENSE("GPL");
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#else /* !MODULE */
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late_initcall(run_all_tests);
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#endif
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