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drm/amd/display: Deprecate DMUB register offload functionality

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[Why]
The DMUB register offload feature should no longer be used.
This was originally a debug feature for DCN21.
No longer applicable to the DMUB programming model.

[How]
Remove DMUB register offload infrastructure including helper
functions, structures, debug options, and register sequence macros.

Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Signed-off-by: Austin Zheng <Austin.Zheng@amd.com>
Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com>
Tested-by: Dan Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Austin Zheng
2026-05-12 16:20:54 -04:00
committed by Alex Deucher
parent 5836e66978
commit 0fde96e06f
20 changed files with 0 additions and 330 deletions
Download Patch File Download Diff File Expand all files Collapse all files

7
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
View File

@@ -13915,13 +13915,6 @@ uint32_t dm_read_reg_func(const struct dc_context *ctx, uint32_t address,
}
#endif
if (ctx->dmub_srv &&
ctx->dmub_srv->reg_helper_offload.gather_in_progress &&
!ctx->dmub_srv->reg_helper_offload.should_burst_write) {
ASSERT(false);
return 0;
}
amdgpu_dm_exit_ips_for_hw_access(ctx->dc);
value = cgs_read_register(ctx->cgs_device, address);

3
drivers/gpu/drm/amd/display/dc/dc.h
View File

@@ -1129,8 +1129,6 @@ struct dc_debug_options {
unsigned int force_fclk_khz;
bool enable_tri_buf;
bool ips_disallow_entry;
bool dmub_offload_enabled;
bool dmcub_emulation;
bool disable_idle_power_optimizations;
unsigned int mall_size_override;
unsigned int mall_additional_timer_percent;
@@ -1332,7 +1330,6 @@ struct dc_init_data {
enum dce_environment dce_environment;
struct dmub_offload_funcs *dmub_if;
struct dc_reg_helper_state *dmub_offload;
struct dc_config flags;
uint64_t log_mask;

12
drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c
View File

@@ -518,9 +518,6 @@ void dc_dmub_srv_query_caps_cmd(struct dc_dmub_srv *dc_dmub_srv)
{
union dmub_rb_cmd cmd = { 0 };
if (dc_dmub_srv->ctx->dc->debug.dmcub_emulation)
return;
memset(&cmd, 0, sizeof(cmd));
/* Prepare fw command */
@@ -1302,9 +1299,6 @@ bool dc_dmub_srv_is_hw_pwr_up(struct dc_dmub_srv *dc_dmub_srv, bool wait)
if (!dc_dmub_srv || !dc_dmub_srv->dmub)
return true;
if (dc_dmub_srv->ctx->dc->debug.dmcub_emulation)
return true;
dc_ctx = dc_dmub_srv->ctx;
if (wait) {
@@ -1345,9 +1339,6 @@ static void dc_dmub_srv_notify_idle(const struct dc *dc, bool allow_idle)
struct dc_dmub_srv *dc_dmub_srv;
union dmub_rb_cmd cmd = {0};
if (dc->debug.dmcub_emulation)
return;
if (!dc->ctx->dmub_srv || !dc->ctx->dmub_srv->dmub)
return;
@@ -1466,9 +1457,6 @@ static void dc_dmub_srv_exit_low_power_state(const struct dc *dc)
struct dc_dmub_srv *dc_dmub_srv;
uint32_t rcg_exit_count = 0, ips1_exit_count = 0, ips2_exit_count = 0, ips1z8_exit_count = 0;
if (dc->debug.dmcub_emulation)
return;
if (!dc->ctx->dmub_srv || !dc->ctx->dmub_srv->dmub)
return;

9
drivers/gpu/drm/amd/display/dc/dc_dmub_srv.h
View File

@@ -37,17 +37,8 @@ struct dc_crtc_timing;
struct dc_state;
struct dc_surface_update;
struct dc_reg_helper_state {
bool gather_in_progress;
uint32_t same_addr_count;
bool should_burst_write;
union dmub_rb_cmd cmd_data;
unsigned int reg_seq_count;
};
struct dc_dmub_srv {
struct dmub_srv *dmub;
struct dc_reg_helper_state reg_helper_offload;
struct dc_context *ctx;
void *dm;

226
drivers/gpu/drm/amd/display/dc/dc_helper.c
View File

@@ -39,53 +39,6 @@
#define DC_LOGGER \
ctx->logger
static inline void submit_dmub_read_modify_write(
struct dc_reg_helper_state *offload,
const struct dc_context *ctx)
{
struct dmub_rb_cmd_read_modify_write *cmd_buf = &offload->cmd_data.read_modify_write;
offload->should_burst_write =
(offload->same_addr_count == (DMUB_READ_MODIFY_WRITE_SEQ__MAX - 1));
cmd_buf->header.payload_bytes =
sizeof(struct dmub_cmd_read_modify_write_sequence) * offload->reg_seq_count;
dc_wake_and_execute_dmub_cmd(ctx, &offload->cmd_data, DM_DMUB_WAIT_TYPE_NO_WAIT);
memset(cmd_buf, 0, sizeof(*cmd_buf));
offload->reg_seq_count = 0;
offload->same_addr_count = 0;
}
static inline void submit_dmub_burst_write(
struct dc_reg_helper_state *offload,
const struct dc_context *ctx)
{
struct dmub_rb_cmd_burst_write *cmd_buf = &offload->cmd_data.burst_write;
cmd_buf->header.payload_bytes =
sizeof(uint32_t) * offload->reg_seq_count;
dc_wake_and_execute_dmub_cmd(ctx, &offload->cmd_data, DM_DMUB_WAIT_TYPE_NO_WAIT);
memset(cmd_buf, 0, sizeof(*cmd_buf));
offload->reg_seq_count = 0;
}
static inline void submit_dmub_reg_wait(
struct dc_reg_helper_state *offload,
const struct dc_context *ctx)
{
struct dmub_rb_cmd_reg_wait *cmd_buf = &offload->cmd_data.reg_wait;
dc_wake_and_execute_dmub_cmd(ctx, &offload->cmd_data, DM_DMUB_WAIT_TYPE_NO_WAIT);
memset(cmd_buf, 0, sizeof(*cmd_buf));
offload->reg_seq_count = 0;
}
struct dc_reg_value_masks {
uint32_t value;
uint32_t mask;
@@ -127,98 +80,6 @@ static void set_reg_field_values(struct dc_reg_value_masks *field_value_mask,
}
}
static void dmub_flush_buffer_execute(
struct dc_reg_helper_state *offload,
const struct dc_context *ctx)
{
submit_dmub_read_modify_write(offload, ctx);
}
static void dmub_flush_burst_write_buffer_execute(
struct dc_reg_helper_state *offload,
const struct dc_context *ctx)
{
submit_dmub_burst_write(offload, ctx);
}
static bool dmub_reg_value_burst_set_pack(const struct dc_context *ctx, uint32_t addr,
uint32_t reg_val)
{
struct dc_reg_helper_state *offload = &ctx->dmub_srv->reg_helper_offload;
struct dmub_rb_cmd_burst_write *cmd_buf = &offload->cmd_data.burst_write;
/* flush command if buffer is full */
if (offload->reg_seq_count == DMUB_BURST_WRITE_VALUES__MAX)
dmub_flush_burst_write_buffer_execute(offload, ctx);
if (offload->cmd_data.cmd_common.header.type == DMUB_CMD__REG_SEQ_BURST_WRITE &&
addr != cmd_buf->addr) {
dmub_flush_burst_write_buffer_execute(offload, ctx);
return false;
}
cmd_buf->header.type = DMUB_CMD__REG_SEQ_BURST_WRITE;
cmd_buf->header.sub_type = 0;
cmd_buf->addr = addr;
cmd_buf->write_values[offload->reg_seq_count] = reg_val;
offload->reg_seq_count++;
return true;
}
static uint32_t dmub_reg_value_pack(const struct dc_context *ctx, uint32_t addr,
struct dc_reg_value_masks *field_value_mask)
{
struct dc_reg_helper_state *offload = &ctx->dmub_srv->reg_helper_offload;
struct dmub_rb_cmd_read_modify_write *cmd_buf = &offload->cmd_data.read_modify_write;
struct dmub_cmd_read_modify_write_sequence *seq;
/* flush command if buffer is full */
if (offload->cmd_data.cmd_common.header.type != DMUB_CMD__REG_SEQ_BURST_WRITE &&
offload->reg_seq_count == DMUB_READ_MODIFY_WRITE_SEQ__MAX)
dmub_flush_buffer_execute(offload, ctx);
if (offload->should_burst_write) {
if (dmub_reg_value_burst_set_pack(ctx, addr, field_value_mask->value))
return field_value_mask->value;
else
offload->should_burst_write = false;
}
/* pack commands */
cmd_buf->header.type = DMUB_CMD__REG_SEQ_READ_MODIFY_WRITE;
cmd_buf->header.sub_type = 0;
seq = &cmd_buf->seq[offload->reg_seq_count];
if (offload->reg_seq_count) {
if (cmd_buf->seq[offload->reg_seq_count - 1].addr == addr)
offload->same_addr_count++;
else
offload->same_addr_count = 0;
}
seq->addr = addr;
seq->modify_mask = field_value_mask->mask;
seq->modify_value = field_value_mask->value;
offload->reg_seq_count++;
return field_value_mask->value;
}
static void dmub_reg_wait_done_pack(const struct dc_context *ctx, uint32_t addr,
uint32_t mask, uint32_t shift, uint32_t condition_value, uint32_t time_out_us)
{
struct dc_reg_helper_state *offload = &ctx->dmub_srv->reg_helper_offload;
struct dmub_rb_cmd_reg_wait *cmd_buf = &offload->cmd_data.reg_wait;
cmd_buf->header.type = DMUB_CMD__REG_REG_WAIT;
cmd_buf->header.sub_type = 0;
cmd_buf->reg_wait.addr = addr;
cmd_buf->reg_wait.condition_field_value = mask & (condition_value << shift);
cmd_buf->reg_wait.mask = mask;
cmd_buf->reg_wait.time_out_us = time_out_us;
}
uint32_t generic_reg_update_ex(const struct dc_context *ctx,
uint32_t addr, int n,
uint8_t shift1, uint32_t mask1, uint32_t field_value1,
@@ -235,11 +96,6 @@ uint32_t generic_reg_update_ex(const struct dc_context *ctx,
va_end(ap);
if (ctx->dmub_srv &&
ctx->dmub_srv->reg_helper_offload.gather_in_progress)
return dmub_reg_value_pack(ctx, addr, &field_value_mask);
/* todo: return void so we can decouple code running in driver from register states */
/* mmio write directly */
reg_val = dm_read_reg(ctx, addr);
reg_val = (reg_val & ~field_value_mask.mask) | field_value_mask.value;
@@ -265,12 +121,6 @@ uint32_t generic_reg_set_ex(const struct dc_context *ctx,
/* mmio write directly */
reg_val = (reg_val & ~field_value_mask.mask) | field_value_mask.value;
if (ctx->dmub_srv &&
ctx->dmub_srv->reg_helper_offload.gather_in_progress) {
return dmub_reg_value_burst_set_pack(ctx, addr, reg_val);
/* todo: return void so we can decouple code running in driver from register states */
}
dm_write_reg(ctx, addr, reg_val);
return reg_val;
}
@@ -434,13 +284,6 @@ void generic_reg_wait(const struct dc_context *ctx,
uint32_t reg_val;
unsigned int i;
if (ctx->dmub_srv &&
ctx->dmub_srv->reg_helper_offload.gather_in_progress) {
dmub_reg_wait_done_pack(ctx, addr, mask, shift, condition_value,
delay_between_poll_us * time_out_num_tries);
return;
}
/*
* Something is terribly wrong if time out is > 3000ms.
* 3000ms is the maximum time needed for SMU to pass values back.
@@ -491,12 +334,6 @@ uint32_t generic_read_indirect_reg(const struct dc_context *ctx,
{
uint32_t value = 0;
// when reg read, there should not be any offload.
if (ctx->dmub_srv &&
ctx->dmub_srv->reg_helper_offload.gather_in_progress) {
ASSERT(false);
}
dm_write_reg(ctx, addr_index, index);
value = dm_read_reg(ctx, addr_data);
@@ -624,69 +461,6 @@ uint32_t generic_indirect_reg_get_sync(const struct dc_context *ctx,
return value;
}
void reg_sequence_start_gather(const struct dc_context *ctx)
{
/* if reg sequence is supported and enabled, set flag to
* indicate we want to have REG_SET, REG_UPDATE macro build
* reg sequence command buffer rather than MMIO directly.
*/
if (ctx->dmub_srv && ctx->dc->debug.dmub_offload_enabled) {
struct dc_reg_helper_state *offload =
&ctx->dmub_srv->reg_helper_offload;
/* caller sequence mismatch. need to debug caller. offload will not work!!! */
ASSERT(!offload->gather_in_progress);
offload->gather_in_progress = true;
}
}
void reg_sequence_start_execute(const struct dc_context *ctx)
{
struct dc_reg_helper_state *offload;
if (!ctx->dmub_srv)
return;
offload = &ctx->dmub_srv->reg_helper_offload;
if (offload && offload->gather_in_progress) {
offload->gather_in_progress = false;
offload->should_burst_write = false;
switch (offload->cmd_data.cmd_common.header.type) {
case DMUB_CMD__REG_SEQ_READ_MODIFY_WRITE:
submit_dmub_read_modify_write(offload, ctx);
break;
case DMUB_CMD__REG_REG_WAIT:
submit_dmub_reg_wait(offload, ctx);
break;
case DMUB_CMD__REG_SEQ_BURST_WRITE:
submit_dmub_burst_write(offload, ctx);
break;
default:
return;
}
}
}
void reg_sequence_wait_done(const struct dc_context *ctx)
{
/* callback to DM to poll for last submission done*/
struct dc_reg_helper_state *offload;
if (!ctx->dmub_srv)
return;
offload = &ctx->dmub_srv->reg_helper_offload;
if (offload &&
ctx->dc->debug.dmub_offload_enabled &&
!ctx->dc->debug.dmcub_emulation) {
dc_dmub_srv_wait_for_idle(ctx->dmub_srv, DM_DMUB_WAIT_TYPE_WAIT, NULL);
}
}
char *dce_version_to_string(const int version)
{
switch (version) {

4
drivers/gpu/drm/amd/display/dc/dm_services.h
View File

@@ -127,10 +127,6 @@ uint32_t generic_reg_update_ex(const struct dc_context *ctx,
struct dc_dmub_srv *dc_dmub_srv_create(struct dc *dc, struct dmub_srv *dmub);
void dc_dmub_srv_destroy(struct dc_dmub_srv **dmub_srv);
void reg_sequence_start_gather(const struct dc_context *ctx);
void reg_sequence_start_execute(const struct dc_context *ctx);
void reg_sequence_wait_done(const struct dc_context *ctx);
#define FD(reg_field) reg_field ## __SHIFT, \
reg_field ## _MASK

5
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c
View File

@@ -397,8 +397,6 @@ void dpp1_cm_program_regamma_lut(struct dpp *dpp_base,
uint32_t i;
struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base);
REG_SEQ_START();
for (i = 0 ; i < num; i++) {
REG_SET(CM_RGAM_LUT_DATA, 0, CM_RGAM_LUT_DATA, rgb[i].red_reg);
REG_SET(CM_RGAM_LUT_DATA, 0, CM_RGAM_LUT_DATA, rgb[i].green_reg);
@@ -408,9 +406,6 @@ void dpp1_cm_program_regamma_lut(struct dpp *dpp_base,
REG_SET(CM_RGAM_LUT_DATA, 0, CM_RGAM_LUT_DATA, rgb[i].delta_green_reg);
REG_SET(CM_RGAM_LUT_DATA, 0, CM_RGAM_LUT_DATA, rgb[i].delta_blue_reg);
}
REG_SEQ_SUBMIT();
REG_SEQ_WAIT_DONE();
}
void dpp1_cm_configure_regamma_lut(

3
drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
View File

@@ -581,9 +581,6 @@ void dcn35_power_down_on_boot(struct dc *dc)
bool dcn35_apply_idle_power_optimizations(struct dc *dc, bool enable)
{
if (dc->debug.dmcub_emulation)
return true;
if (enable) {
uint32_t num_active_edp = 0;
int i;

19
drivers/gpu/drm/amd/display/dc/inc/reg_helper.h
View File

@@ -536,23 +536,4 @@ uint32_t generic_indirect_reg_update_ex_sync(const struct dc_context *ctx,
uint8_t shift1, uint32_t mask1, uint32_t field_value1,
...);
/* register offload macros
*
* instead of MMIO to register directly, in some cases we want
* to gather register sequence and execute the register sequence
* from another thread so we optimize time required for lengthy ops
*/
/* start gathering register sequence */
#define REG_SEQ_START() \
reg_sequence_start_gather(CTX)
/* start execution of register sequence gathered since REG_SEQ_START */
#define REG_SEQ_SUBMIT() \
reg_sequence_start_execute(CTX)
/* wait for the last REG_SEQ_SUBMIT to finish */
#define REG_SEQ_WAIT_DONE() \
reg_sequence_wait_done(CTX)
#endif /* DRIVERS_GPU_DRM_AMD_DC_DEV_DC_INC_REG_HELPER_H_ */

4
drivers/gpu/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.c
View File

@@ -380,7 +380,6 @@ static void mpc20_program_ogam_pwl(
struct dcn20_mpc *mpc20 = TO_DCN20_MPC(mpc);
PERF_TRACE();
REG_SEQ_START();
for (i = 0 ; i < num; i++) {
REG_SET(MPCC_OGAM_LUT_DATA[mpcc_id], 0, MPCC_OGAM_LUT_DATA, rgb[i].red_reg);
@@ -395,9 +394,6 @@ static void mpc20_program_ogam_pwl(
MPCC_OGAM_LUT_DATA, rgb[i].delta_blue_reg);
}
REG_SEQ_SUBMIT();
PERF_TRACE();
REG_SEQ_WAIT_DONE();
PERF_TRACE();
}

5
drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.c
View File

@@ -539,16 +539,11 @@ static bool optc1_enable_crtc(struct timing_generator *optc)
REG_UPDATE(CONTROL,
VTG0_ENABLE, 1);
REG_SEQ_START();
/* Enable CRTC */
REG_UPDATE_2(OTG_CONTROL,
OTG_DISABLE_POINT_CNTL, 3,
OTG_MASTER_EN, 1);
REG_SEQ_SUBMIT();
REG_SEQ_WAIT_DONE();
return true;
}

5
drivers/gpu/drm/amd/display/dc/optc/dcn20/dcn20_optc.c
View File

@@ -63,16 +63,11 @@ bool optc2_enable_crtc(struct timing_generator *optc)
REG_UPDATE(CONTROL,
VTG0_ENABLE, 1);
REG_SEQ_START();
/* Enable CRTC */
REG_UPDATE_2(OTG_CONTROL,
OTG_DISABLE_POINT_CNTL, 3,
OTG_MASTER_EN, 1);
REG_SEQ_SUBMIT();
REG_SEQ_WAIT_DONE();
return true;
}

5
drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.c
View File

@@ -105,16 +105,11 @@ static bool optc31_enable_crtc(struct timing_generator *optc)
REG_UPDATE(CONTROL,
VTG0_ENABLE, 1);
REG_SEQ_START();
/* Enable CRTC */
REG_UPDATE_2(OTG_CONTROL,
OTG_DISABLE_POINT_CNTL, 2,
OTG_MASTER_EN, 1);
REG_SEQ_SUBMIT();
REG_SEQ_WAIT_DONE();
return true;
}

5
drivers/gpu/drm/amd/display/dc/optc/dcn314/dcn314_optc.c
View File

@@ -115,16 +115,11 @@ static bool optc314_enable_crtc(struct timing_generator *optc)
REG_UPDATE(CONTROL,
VTG0_ENABLE, 1);
REG_SEQ_START();
/* Enable CRTC */
REG_UPDATE_2(OTG_CONTROL,
OTG_DISABLE_POINT_CNTL, 2,
OTG_MASTER_EN, 1);
REG_SEQ_SUBMIT();
REG_SEQ_WAIT_DONE();
return true;
}

5
drivers/gpu/drm/amd/display/dc/optc/dcn32/dcn32_optc.c
View File

@@ -155,16 +155,11 @@ static bool optc32_enable_crtc(struct timing_generator *optc)
REG_UPDATE(CONTROL,
VTG0_ENABLE, 1);
REG_SEQ_START();
/* Enable CRTC */
REG_UPDATE_2(OTG_CONTROL,
OTG_DISABLE_POINT_CNTL, 2,
OTG_MASTER_EN, 1);
REG_SEQ_SUBMIT();
REG_SEQ_WAIT_DONE();
return true;
}

5
drivers/gpu/drm/amd/display/dc/optc/dcn35/dcn35_optc.c
View File

@@ -122,16 +122,11 @@ static bool optc35_enable_crtc(struct timing_generator *optc)
REG_UPDATE(CONTROL,
VTG0_ENABLE, 1);
REG_SEQ_START();
/* Enable CRTC */
REG_UPDATE_2(OTG_CONTROL,
OTG_DISABLE_POINT_CNTL, 2,
OTG_MASTER_EN, 1);
REG_SEQ_SUBMIT();
REG_SEQ_WAIT_DONE();
return true;
}

5
drivers/gpu/drm/amd/display/dc/optc/dcn401/dcn401_optc.c
View File

@@ -189,16 +189,11 @@ bool optc401_enable_crtc(struct timing_generator *optc)
REG_UPDATE(CONTROL,
VTG0_ENABLE, 1);
REG_SEQ_START();
/* Enable CRTC */
REG_UPDATE_2(OTG_CONTROL,
OTG_DISABLE_POINT_CNTL, 2,
OTG_MASTER_EN, 1);
REG_SEQ_SUBMIT();
REG_SEQ_WAIT_DONE();
return true;
}

1
drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c
View File

@@ -819,7 +819,6 @@ static const struct dc_debug_options debug_defaults_drv = {
.enable_hpo_pg_support = false,
.enable_single_display_2to1_odm_policy = true,
.disable_idle_power_optimizations = false,
.dmcub_emulation = false,
.disable_boot_optimizations = false,
.disable_unbounded_requesting = false,
.disable_mem_low_power = false,

1
drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c
View File

@@ -799,7 +799,6 @@ static const struct dc_debug_options debug_defaults_drv = {
.enable_hpo_pg_support = false,
.enable_single_display_2to1_odm_policy = true,
.disable_idle_power_optimizations = false,
.dmcub_emulation = false,
.disable_boot_optimizations = false,
.disable_unbounded_requesting = false,
.disable_mem_low_power = false,

1
drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c
View File

@@ -806,7 +806,6 @@ static const struct dc_debug_options debug_defaults_drv = {
.enable_hpo_pg_support = false,
.enable_single_display_2to1_odm_policy = true,
.disable_idle_power_optimizations = false,
.dmcub_emulation = false,
.disable_boot_optimizations = false,
.disable_unbounded_requesting = false,
.disable_mem_low_power = false,