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ARM: dts: exynos: Use labels instead of full paths in exynos4210-trats

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Extend camera and fimc nodes by labels, not by full path in Exynos
4210 Trats board.  This avoids error-prone redefinition of nodes.

Signed-off-by: Maciej Purski <m.purski@samsung.com>
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
This commit is contained in:
Maciej Purski
2018-02-05 08:57:03 +01:00
committed by Krzysztof Kozlowski
parent e030be47ac
commit 0f895e4ef7
1 changed files with 37 additions and 36 deletions
Download Patch File Download Diff File Expand all files Collapse all files

73
arch/arm/boot/dts/exynos4210-trats.dts
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@@ -148,43 +148,12 @@ map1 {
};
};
camera {
pinctrl-names = "default";
pinctrl-0 = <>;
status = "okay";
};
fimc_0: fimc@11800000 {
status = "okay";
assigned-clocks = <&clock CLK_MOUT_FIMC0>,
<&clock CLK_SCLK_FIMC0>;
assigned-clock-parents = <&clock CLK_SCLK_MPLL>;
assigned-clock-rates = <0>, <160000000>;
};
fimc_1: fimc@11810000 {
status = "okay";
assigned-clocks = <&clock CLK_MOUT_FIMC1>,
<&clock CLK_SCLK_FIMC1>;
assigned-clock-parents = <&clock CLK_SCLK_MPLL>;
assigned-clock-rates = <0>, <160000000>;
};
fimc_2: fimc@11820000 {
status = "okay";
assigned-clocks = <&clock CLK_MOUT_FIMC2>,
<&clock CLK_SCLK_FIMC2>;
assigned-clock-parents = <&clock CLK_SCLK_MPLL>;
assigned-clock-rates = <0>, <160000000>;
};
fimc_3: fimc@11830000 {
status = "okay";
assigned-clocks = <&clock CLK_MOUT_FIMC3>,
<&clock CLK_SCLK_FIMC3>;
assigned-clock-parents = <&clock CLK_SCLK_MPLL>;
assigned-clock-rates = <0>, <160000000>;
};
};
&camera {
pinctrl-names = "default";
pinctrl-0 = <>;
status = "okay";
};
&cpu0 {
@@ -234,6 +203,38 @@ &exynos_usbphy {
vbus-supply = <&safe1_sreg>;
};
&fimc_0 {
status = "okay";
assigned-clocks = <&clock CLK_MOUT_FIMC0>,
<&clock CLK_SCLK_FIMC0>;
assigned-clock-parents = <&clock CLK_SCLK_MPLL>;
assigned-clock-rates = <0>, <160000000>;
};
&fimc_1 {
status = "okay";
assigned-clocks = <&clock CLK_MOUT_FIMC1>,
<&clock CLK_SCLK_FIMC1>;
assigned-clock-parents = <&clock CLK_SCLK_MPLL>;
assigned-clock-rates = <0>, <160000000>;
};
&fimc_2 {
status = "okay";
assigned-clocks = <&clock CLK_MOUT_FIMC2>,
<&clock CLK_SCLK_FIMC2>;
assigned-clock-parents = <&clock CLK_SCLK_MPLL>;
assigned-clock-rates = <0>, <160000000>;
};
&fimc_3 {
status = "okay";
assigned-clocks = <&clock CLK_MOUT_FIMC3>,
<&clock CLK_SCLK_FIMC3>;
assigned-clock-parents = <&clock CLK_SCLK_MPLL>;
assigned-clock-rates = <0>, <160000000>;
};
&fimd {
status = "okay";
};