mirrors/linux
1
0
Fork 0
mirror of https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git synced 2026-05-03 17:04:50 -04:00
Code Issues Packages Projects Releases Wiki Activity

drm/amd/display: add scaler control for dcn32

Browse Source 
[WHY]
It will introduce the extra warnning log on some asic
that doesn't register

[HOW]
Add the register on dcn32

Reviewed-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com>
Signed-off-by: Zhikai Zhai <zhikai.zhai@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Zhikai Zhai
2023-03-15 11:16:12 +08:00
committed by Alex Deucher
parent abaeafb1b1
commit 0efa703568
1 changed files with 1 additions and 0 deletions
Download Patch File Download Diff File Expand all files Collapse all files

1
drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.h
View File

@@ -472,6 +472,7 @@ double dcn32_determine_max_vratio_prefetch(struct dc *dc, struct dc_state *conte
SRI_ARR(OTG_H_BLANK, DSCL, id), SRI_ARR(OTG_V_BLANK, DSCL, id), \
SRI_ARR(SCL_MODE, DSCL, id), SRI_ARR(LB_DATA_FORMAT, DSCL, id), \
SRI_ARR(LB_MEMORY_CTRL, DSCL, id), SRI_ARR(DSCL_AUTOCAL, DSCL, id), \
SRI_ARR(DSCL_CONTROL, DSCL, id), \
SRI_ARR(SCL_TAP_CONTROL, DSCL, id), \
SRI_ARR(SCL_COEF_RAM_TAP_SELECT, DSCL, id), \
SRI_ARR(SCL_COEF_RAM_TAP_DATA, DSCL, id), \