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ARM: dts: qcom: sdx65: Add QPIC NAND support

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Add devicetree node to enable support for QPIC
NAND controller on Qualcomm SDX65 platform.
Since there is no "aon" clock in SDX65, a dummy
clock is provided.

Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Signed-off-by: Kaushal Kumar <quic_kaushalk@quicinc.com>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/1651511286-18690-3-git-send-email-quic_kaushalk@quicinc.com
This commit is contained in:
Kaushal Kumar
2022-05-02 10:08:04 -07:00
committed by Bjorn Andersson
parent ab11b74d87
commit 0ec15b6f76
1 changed files with 22 additions and 0 deletions
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22
arch/arm/boot/dts/qcom-sdx65.dtsi
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@@ -37,6 +37,12 @@ sleep_clk: sleep-clk {
clock-output-names = "sleep_clk";
#clock-cells = <0>;
};
nand_clk_dummy: nand-clk-dummy {
compatible = "fixed-clock";
clock-frequency = <32764>;
#clock-cells = <0>;
};
};
cpus {
@@ -204,6 +210,22 @@ qpic_bam: dma-controller@1b04000 {
status = "disabled";
};
qpic_nand: nand-controller@1b30000 {
compatible = "qcom,sdx55-nand";
reg = <0x01b30000 0x10000>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&rpmhcc RPMH_QPIC_CLK>,
<&nand_clk_dummy>;
clock-names = "core", "aon";
dmas = <&qpic_bam 0>,
<&qpic_bam 1>,
<&qpic_bam 2>;
dma-names = "tx", "rx", "cmd";
status = "disabled";
};
tcsr_mutex: hwlock@1f40000 {
compatible = "qcom,tcsr-mutex";
reg = <0x01f40000 0x40000>;