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arm64: dts: imx8qxp-mek: add fec2 support

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Add fec2 and related nodes.

Signed-off-by: Frank Li <Frank.Li@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
This commit is contained in:
Frank Li
2025-10-29 15:54:44 -04:00
committed by Shawn Guo
parent f4dcaab01b
commit 0e2dbdcfad
1 changed files with 43 additions and 0 deletions
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43
arch/arm64/boot/dts/freescale/imx8qxp-mek.dts
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@@ -219,6 +219,15 @@ reg_can_stby: regulator-can-stby {
vin-supply = <&reg_can_en>;
};
reg_fec2_supply: regulator-fec2_nvcc {
compatible = "regulator-fixed";
regulator-name = "fec2_nvcc";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
gpio = <&max7322 0 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
reg_usb_otg1_vbus: regulator-usbotg1-vbus {
compatible = "regulator-fixed";
regulator-max-microvolt = <5000000>;
@@ -417,9 +426,26 @@ ethphy0: ethernet-phy@0 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <0>;
};
ethphy1: ethernet-phy@1 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <1>;
};
};
};
&fec2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_fec2>;
phy-mode = "rgmii-id";
phy-handle = <&ethphy1>;
phy-supply = <&reg_fec2_supply>;
fsl,magic-packet;
nvmem-cells = <&fec_mac1>;
nvmem-cell-names = "mac-address";
status = "disabled";
};
&i2c1 {
#address-cells = <1>;
#size-cells = <0>;
@@ -884,6 +910,23 @@ IMX8QXP_ENET0_RGMII_RXD3_CONN_ENET0_RGMII_RXD3 0x06000020
>;
};
pinctrl_fec2: fec2grp {
fsl,pins = <
IMX8QXP_ESAI0_SCKR_CONN_ENET1_RGMII_TX_CTL 0x00000060
IMX8QXP_ESAI0_FSR_CONN_ENET1_RGMII_TXC 0x00000060
IMX8QXP_ESAI0_TX4_RX1_CONN_ENET1_RGMII_TXD0 0x00000060
IMX8QXP_ESAI0_TX5_RX0_CONN_ENET1_RGMII_TXD1 0x00000060
IMX8QXP_ESAI0_FST_CONN_ENET1_RGMII_TXD2 0x00000060
IMX8QXP_ESAI0_SCKT_CONN_ENET1_RGMII_TXD3 0x00000060
IMX8QXP_ESAI0_TX0_CONN_ENET1_RGMII_RXC 0x00000060
IMX8QXP_SPDIF0_TX_CONN_ENET1_RGMII_RX_CTL 0x00000060
IMX8QXP_SPDIF0_RX_CONN_ENET1_RGMII_RXD0 0x00000060
IMX8QXP_ESAI0_TX3_RX2_CONN_ENET1_RGMII_RXD1 0x00000060
IMX8QXP_ESAI0_TX2_RX3_CONN_ENET1_RGMII_RXD2 0x00000060
IMX8QXP_ESAI0_TX1_CONN_ENET1_RGMII_RXD3 0x00000060
>;
};
pinctrl_flexcan1: flexcan0grp {
fsl,pins = <
IMX8QXP_FLEXCAN0_TX_ADMA_FLEXCAN0_TX 0x21