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synced 2026-05-16 05:31:37 -04:00
Merge branch 'bnge-fixes'
Vikas Gupta says:
====================
bnge fixes
Patch-1:
Due to wrong HWRM sequence, driver do not get the correct
information regarding resources and capabilities.
The patch fixes the initial HWRM sequence.
Patch-2:
Remove the unsupported backing store type initialization, which is
not supported in Thor Ultra devices.
====================
Link: https://patch.msgid.link/20260418023438.1597876-1-vikas.gupta@broadcom.com
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
This commit is contained in:
@@ -74,6 +74,13 @@ static int bnge_func_qcaps(struct bnge_dev *bd)
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return rc;
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}
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return 0;
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}
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static int bnge_func_qrcaps_qcfg(struct bnge_dev *bd)
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{
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int rc;
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rc = bnge_hwrm_func_resc_qcaps(bd);
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if (rc) {
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dev_err(bd->dev, "query resc caps failure rc: %d\n", rc);
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@@ -133,23 +140,28 @@ static int bnge_fw_register_dev(struct bnge_dev *bd)
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bnge_hwrm_fw_set_time(bd);
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rc = bnge_hwrm_func_drv_rgtr(bd);
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/* Get the resources and configuration from firmware */
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rc = bnge_func_qcaps(bd);
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if (rc) {
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dev_err(bd->dev, "Failed to rgtr with firmware rc: %d\n", rc);
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dev_err(bd->dev, "Failed querying caps rc: %d\n", rc);
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return rc;
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}
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rc = bnge_alloc_ctx_mem(bd);
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if (rc) {
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dev_err(bd->dev, "Failed to allocate ctx mem rc: %d\n", rc);
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goto err_func_unrgtr;
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goto err_free_ctx_mem;
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}
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/* Get the resources and configuration from firmware */
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rc = bnge_func_qcaps(bd);
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rc = bnge_hwrm_func_drv_rgtr(bd);
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if (rc) {
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dev_err(bd->dev, "Failed initial configuration rc: %d\n", rc);
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rc = -ENODEV;
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dev_err(bd->dev, "Failed to rgtr with firmware rc: %d\n", rc);
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goto err_free_ctx_mem;
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}
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rc = bnge_func_qrcaps_qcfg(bd);
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if (rc) {
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dev_err(bd->dev, "Failed querying resources rc: %d\n", rc);
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goto err_func_unrgtr;
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}
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@@ -158,7 +170,9 @@ static int bnge_fw_register_dev(struct bnge_dev *bd)
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return 0;
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err_func_unrgtr:
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bnge_fw_unregister_dev(bd);
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bnge_hwrm_func_drv_unrgtr(bd);
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err_free_ctx_mem:
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bnge_free_ctx_mem(bd);
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return rc;
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}
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@@ -324,7 +324,6 @@ int bnge_alloc_ctx_mem(struct bnge_dev *bd)
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u32 l2_qps, qp1_qps, max_qps;
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u32 ena, entries_sp, entries;
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u32 srqs, max_srqs, min;
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u32 num_mr, num_ah;
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u32 extra_srqs = 0;
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u32 extra_qps = 0;
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u32 fast_qpmd_qps;
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@@ -390,21 +389,6 @@ int bnge_alloc_ctx_mem(struct bnge_dev *bd)
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if (!bnge_is_roce_en(bd))
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goto skip_rdma;
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ctxm = &ctx->ctx_arr[BNGE_CTX_MRAV];
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/* 128K extra is needed to accommodate static AH context
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* allocation by f/w.
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*/
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num_mr = min_t(u32, ctxm->max_entries / 2, 1024 * 256);
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num_ah = min_t(u32, num_mr, 1024 * 128);
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ctxm->split_entry_cnt = BNGE_CTX_MRAV_AV_SPLIT_ENTRY + 1;
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if (!ctxm->mrav_av_entries || ctxm->mrav_av_entries > num_ah)
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ctxm->mrav_av_entries = num_ah;
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rc = bnge_setup_ctxm_pg_tbls(bd, ctxm, num_mr + num_ah, 2);
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if (rc)
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return rc;
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ena |= FUNC_BACKING_STORE_CFG_REQ_ENABLES_MRAV;
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ctxm = &ctx->ctx_arr[BNGE_CTX_TIM];
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rc = bnge_setup_ctxm_pg_tbls(bd, ctxm, l2_qps + qp1_qps + extra_qps, 1);
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if (rc)
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