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staging: comedi: hwrdv_apci3120: absorb private header
The header file hwdrv_apci3120.h is only included by the source file hwrdv_apci3120.c. Absorb the header into the source and delete the header. Signed-off-by: H Hartley Sweeten <hsweeten@visionengravers.com> Cc: Ian Abbott <abbotti@mev.co.uk> Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This commit is contained in:
H Hartley Sweeten
committed by
Greg Kroah-Hartman
Greg Kroah-Hartman
parent
8f8a353479
commit
0d0c706d46
@@ -44,7 +44,173 @@ You should also find the complete GPL in the COPYING file accompanying this sour
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+----------+-----------+------------------------------------------------+
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*/
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#include "hwdrv_apci3120.h"
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/* used for test on mixture of BIP/UNI ranges */
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#define APCI3120_BIPOLAR_RANGES 4
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#define APCI3120_ADDRESS_RANGE 16
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#define APCI3120_DISABLE 0
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#define APCI3120_ENABLE 1
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#define APCI3120_START 1
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#define APCI3120_STOP 0
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#define APCI3120_EOC_MODE 1
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#define APCI3120_EOS_MODE 2
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#define APCI3120_DMA_MODE 3
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/* DIGITAL INPUT-OUTPUT DEFINE */
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#define APCI3120_DIGITAL_OUTPUT 0x0d
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#define APCI3120_RD_STATUS 0x02
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#define APCI3120_RD_FIFO 0x00
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/* digital output insn_write ON /OFF selection */
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#define APCI3120_SET4DIGITALOUTPUTON 1
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#define APCI3120_SET4DIGITALOUTPUTOFF 0
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/* analog output SELECT BIT */
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#define APCI3120_ANALOG_OP_CHANNEL_1 0x0000
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#define APCI3120_ANALOG_OP_CHANNEL_2 0x4000
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#define APCI3120_ANALOG_OP_CHANNEL_3 0x8000
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#define APCI3120_ANALOG_OP_CHANNEL_4 0xc000
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#define APCI3120_ANALOG_OP_CHANNEL_5 0x0000
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#define APCI3120_ANALOG_OP_CHANNEL_6 0x4000
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#define APCI3120_ANALOG_OP_CHANNEL_7 0x8000
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#define APCI3120_ANALOG_OP_CHANNEL_8 0xc000
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/* Enable external trigger bit in nWrAddress */
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#define APCI3120_ENABLE_EXT_TRIGGER 0x8000
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/* ANALOG OUTPUT AND INPUT DEFINE */
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#define APCI3120_UNIPOLAR 0x80
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#define APCI3120_BIPOLAR 0x00
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#define APCI3120_ANALOG_OUTPUT_1 0x08
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#define APCI3120_ANALOG_OUTPUT_2 0x0a
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#define APCI3120_1_GAIN 0x00
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#define APCI3120_2_GAIN 0x10
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#define APCI3120_5_GAIN 0x20
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#define APCI3120_10_GAIN 0x30
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#define APCI3120_SEQ_RAM_ADDRESS 0x06
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#define APCI3120_RESET_FIFO 0x0c
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#define APCI3120_TIMER_0_MODE_2 0x01
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#define APCI3120_TIMER_0_MODE_4 0x2
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#define APCI3120_SELECT_TIMER_0_WORD 0x00
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#define APCI3120_ENABLE_TIMER0 0x1000
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#define APCI3120_CLEAR_PR 0xf0ff
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#define APCI3120_CLEAR_PA 0xfff0
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#define APCI3120_CLEAR_PA_PR (APCI3120_CLEAR_PR & APCI3120_CLEAR_PA)
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/* nWrMode_Select */
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#define APCI3120_ENABLE_SCAN 0x8
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#define APCI3120_DISABLE_SCAN (~APCI3120_ENABLE_SCAN)
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#define APCI3120_ENABLE_EOS_INT 0x2
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#define APCI3120_DISABLE_EOS_INT (~APCI3120_ENABLE_EOS_INT)
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#define APCI3120_ENABLE_EOC_INT 0x1
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#define APCI3120_DISABLE_EOC_INT (~APCI3120_ENABLE_EOC_INT)
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#define APCI3120_DISABLE_ALL_INTERRUPT_WITHOUT_TIMER \
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(APCI3120_DISABLE_EOS_INT & APCI3120_DISABLE_EOC_INT)
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#define APCI3120_DISABLE_ALL_INTERRUPT \
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(APCI3120_DISABLE_TIMER_INT & APCI3120_DISABLE_EOS_INT & APCI3120_DISABLE_EOC_INT)
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/* status register bits */
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#define APCI3120_EOC 0x8000
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#define APCI3120_EOS 0x2000
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/* software trigger dummy register */
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#define APCI3120_START_CONVERSION 0x02
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/* TIMER DEFINE */
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#define APCI3120_QUARTZ_A 70
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#define APCI3120_QUARTZ_B 50
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#define APCI3120_TIMER 1
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#define APCI3120_WATCHDOG 2
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#define APCI3120_TIMER_DISABLE 0
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#define APCI3120_TIMER_ENABLE 1
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#define APCI3120_ENABLE_TIMER2 0x4000
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#define APCI3120_DISABLE_TIMER2 (~APCI3120_ENABLE_TIMER2)
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#define APCI3120_ENABLE_TIMER_INT 0x04
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#define APCI3120_DISABLE_TIMER_INT (~APCI3120_ENABLE_TIMER_INT)
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#define APCI3120_WRITE_MODE_SELECT 0x0e
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#define APCI3120_SELECT_TIMER_0_WORD 0x00
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#define APCI3120_SELECT_TIMER_1_WORD 0x01
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#define APCI3120_TIMER_1_MODE_2 0x4
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/* $$ BIT FOR MODE IN nCsTimerCtr1 */
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#define APCI3120_TIMER_2_MODE_0 0x0
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#define APCI3120_TIMER_2_MODE_2 0x10
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#define APCI3120_TIMER_2_MODE_5 0x30
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/* $$ BIT FOR MODE IN nCsTimerCtr0 */
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#define APCI3120_SELECT_TIMER_2_LOW_WORD 0x02
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#define APCI3120_SELECT_TIMER_2_HIGH_WORD 0x03
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#define APCI3120_TIMER_CRT0 0x0d
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#define APCI3120_TIMER_CRT1 0x0c
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#define APCI3120_TIMER_VALUE 0x04
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#define APCI3120_TIMER_STATUS_REGISTER 0x0d
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#define APCI3120_RD_STATUS 0x02
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#define APCI3120_WR_ADDRESS 0x00
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#define APCI3120_ENABLE_WATCHDOG 0x20
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#define APCI3120_DISABLE_WATCHDOG (~APCI3120_ENABLE_WATCHDOG)
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#define APCI3120_ENABLE_TIMER_COUNTER 0x10
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#define APCI3120_DISABLE_TIMER_COUNTER (~APCI3120_ENABLE_TIMER_COUNTER)
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#define APCI3120_FC_TIMER 0x1000
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#define APCI3120_ENABLE_TIMER0 0x1000
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#define APCI3120_ENABLE_TIMER1 0x2000
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#define APCI3120_ENABLE_TIMER2 0x4000
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#define APCI3120_DISABLE_TIMER0 (~APCI3120_ENABLE_TIMER0)
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#define APCI3120_DISABLE_TIMER1 (~APCI3120_ENABLE_TIMER1)
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#define APCI3120_DISABLE_TIMER2 (~APCI3120_ENABLE_TIMER2)
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#define APCI3120_TIMER2_SELECT_EOS 0xc0
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#define APCI3120_COUNTER 3
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#define APCI3120_DISABLE_ALL_TIMER (APCI3120_DISABLE_TIMER0 & \
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APCI3120_DISABLE_TIMER1 & \
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APCI3120_DISABLE_TIMER2)
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#define MAX_ANALOGINPUT_CHANNELS 32
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struct str_AnalogReadInformation {
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/* EOC or EOS */
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unsigned char b_Type;
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/* Interrupt use or not */
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unsigned char b_InterruptFlag;
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/* Selection of the conversion time */
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unsigned int ui_ConvertTiming;
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/* Number of channel to read */
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unsigned char b_NbrOfChannel;
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/* Number of the channel to be read */
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unsigned int ui_ChannelList[MAX_ANALOGINPUT_CHANNELS];
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/* Gain of each channel */
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unsigned int ui_RangeList[MAX_ANALOGINPUT_CHANNELS];
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};
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/* ANALOG INPUT RANGE */
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static const struct comedi_lrange range_apci3120_ai = {
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8, {
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BIP_RANGE(10),
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BIP_RANGE(5),
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BIP_RANGE(2),
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BIP_RANGE(1),
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UNI_RANGE(10),
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UNI_RANGE(5),
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UNI_RANGE(2),
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UNI_RANGE(1)
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}
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};
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/* ANALOG OUTPUT RANGE */
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static const struct comedi_lrange range_apci3120_ao = {
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2, {
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BIP_RANGE(10),
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UNI_RANGE(10)
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}
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};
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static unsigned int ui_Temp;
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/* FUNCTION DEFINITIONS */
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@@ -1,176 +0,0 @@
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/* hwdrv_apci3120.h */
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/*
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* Copyright (C) 2004,2005 ADDI-DATA GmbH for the source code of this module.
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*
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* ADDI-DATA GmbH
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* Dieselstrasse 3
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* D-77833 Ottersweier
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* Tel: +19(0)7223/9493-0
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* Fax: +49(0)7223/9493-92
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* http://www.addi-data.com
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* info@addi-data.com
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the Free
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* Software Foundation; either version 2 of the License, or (at your option)
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* any later version.
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*/
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/* comedi related defines */
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/* ANALOG INPUT RANGE */
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static const struct comedi_lrange range_apci3120_ai = { 8, {
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BIP_RANGE(10),
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BIP_RANGE(5),
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BIP_RANGE(2),
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BIP_RANGE(1),
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UNI_RANGE(10),
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UNI_RANGE(5),
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UNI_RANGE(2),
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UNI_RANGE(1)
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}
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};
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/* ANALOG OUTPUT RANGE */
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static const struct comedi_lrange range_apci3120_ao = { 2, {
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BIP_RANGE(10),
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UNI_RANGE(10)
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}
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};
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#define APCI3120_BIPOLAR_RANGES 4 /* used for test on mixture of BIP/UNI ranges */
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#define APCI3120_ADDRESS_RANGE 16
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#define APCI3120_DISABLE 0
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#define APCI3120_ENABLE 1
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#define APCI3120_START 1
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#define APCI3120_STOP 0
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#define APCI3120_EOC_MODE 1
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#define APCI3120_EOS_MODE 2
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#define APCI3120_DMA_MODE 3
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/* DIGITAL INPUT-OUTPUT DEFINE */
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#define APCI3120_DIGITAL_OUTPUT 0x0D
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#define APCI3120_RD_STATUS 0x02
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#define APCI3120_RD_FIFO 0x00
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/* digital output insn_write ON /OFF selection */
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#define APCI3120_SET4DIGITALOUTPUTON 1
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#define APCI3120_SET4DIGITALOUTPUTOFF 0
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/* analog output SELECT BIT */
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#define APCI3120_ANALOG_OP_CHANNEL_1 0x0000
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#define APCI3120_ANALOG_OP_CHANNEL_2 0x4000
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#define APCI3120_ANALOG_OP_CHANNEL_3 0x8000
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#define APCI3120_ANALOG_OP_CHANNEL_4 0xC000
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#define APCI3120_ANALOG_OP_CHANNEL_5 0x0000
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#define APCI3120_ANALOG_OP_CHANNEL_6 0x4000
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#define APCI3120_ANALOG_OP_CHANNEL_7 0x8000
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#define APCI3120_ANALOG_OP_CHANNEL_8 0xC000
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/* Enable external trigger bit in nWrAddress */
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#define APCI3120_ENABLE_EXT_TRIGGER 0x8000
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/* ANALOG OUTPUT AND INPUT DEFINE */
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#define APCI3120_UNIPOLAR 0x80 /* $$ RAM sequence polarity BIT */
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#define APCI3120_BIPOLAR 0x00 /* $$ RAM sequence polarity BIT */
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#define APCI3120_ANALOG_OUTPUT_1 0x08 /* (ADDRESS ) */
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#define APCI3120_ANALOG_OUTPUT_2 0x0A /* (ADDRESS ) */
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#define APCI3120_1_GAIN 0x00 /* $$ RAM sequence Gain Bits for gain 1 */
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#define APCI3120_2_GAIN 0x10 /* $$ RAM sequence Gain Bits for gain 2 */
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#define APCI3120_5_GAIN 0x20 /* $$ RAM sequence Gain Bits for gain 5 */
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#define APCI3120_10_GAIN 0x30 /* $$ RAM sequence Gain Bits for gain 10 */
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#define APCI3120_SEQ_RAM_ADDRESS 0x06 /* $$ EARLIER NAMED APCI3120_FIFO_ADDRESS */
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#define APCI3120_RESET_FIFO 0x0C /* (ADDRESS) */
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#define APCI3120_TIMER_0_MODE_2 0x01 /* $$ Bits for timer mode */
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#define APCI3120_TIMER_0_MODE_4 0x2
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#define APCI3120_SELECT_TIMER_0_WORD 0x00
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#define APCI3120_ENABLE_TIMER0 0x1000 /* $$Gatebit 0 in nWrAddress */
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#define APCI3120_CLEAR_PR 0xF0FF
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#define APCI3120_CLEAR_PA 0xFFF0
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#define APCI3120_CLEAR_PA_PR (APCI3120_CLEAR_PR & APCI3120_CLEAR_PA)
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/* nWrMode_Select */
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#define APCI3120_ENABLE_SCAN 0x8 /* $$ bit in nWrMode_Select */
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#define APCI3120_DISABLE_SCAN (~APCI3120_ENABLE_SCAN)
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#define APCI3120_ENABLE_EOS_INT 0x2 /* $$ bit in nWrMode_Select */
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#define APCI3120_DISABLE_EOS_INT (~APCI3120_ENABLE_EOS_INT)
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#define APCI3120_ENABLE_EOC_INT 0x1
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#define APCI3120_DISABLE_EOC_INT (~APCI3120_ENABLE_EOC_INT)
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#define APCI3120_DISABLE_ALL_INTERRUPT_WITHOUT_TIMER (APCI3120_DISABLE_EOS_INT & APCI3120_DISABLE_EOC_INT)
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#define APCI3120_DISABLE_ALL_INTERRUPT (APCI3120_DISABLE_TIMER_INT & APCI3120_DISABLE_EOS_INT & APCI3120_DISABLE_EOC_INT)
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/* status register bits */
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#define APCI3120_EOC 0x8000
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#define APCI3120_EOS 0x2000
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/* software trigger dummy register */
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#define APCI3120_START_CONVERSION 0x02 /* (ADDRESS) */
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/* TIMER DEFINE */
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#define APCI3120_QUARTZ_A 70
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#define APCI3120_QUARTZ_B 50
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#define APCI3120_TIMER 1
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#define APCI3120_WATCHDOG 2
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#define APCI3120_TIMER_DISABLE 0
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#define APCI3120_TIMER_ENABLE 1
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#define APCI3120_ENABLE_TIMER2 0x4000 /* $$ gatebit 2 in nWrAddress */
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#define APCI3120_DISABLE_TIMER2 (~APCI3120_ENABLE_TIMER2)
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#define APCI3120_ENABLE_TIMER_INT 0x04 /* $$ ENAIRQ_FC_Bit in nWrModeSelect */
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#define APCI3120_DISABLE_TIMER_INT (~APCI3120_ENABLE_TIMER_INT)
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#define APCI3120_WRITE_MODE_SELECT 0x0E /* (ADDRESS) */
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#define APCI3120_SELECT_TIMER_0_WORD 0x00
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#define APCI3120_SELECT_TIMER_1_WORD 0x01
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#define APCI3120_TIMER_1_MODE_2 0x4
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/* $$ BIT FOR MODE IN nCsTimerCtr1 */
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#define APCI3120_TIMER_2_MODE_0 0x0
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#define APCI3120_TIMER_2_MODE_2 0x10
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#define APCI3120_TIMER_2_MODE_5 0x30
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/* $$ BIT FOR MODE IN nCsTimerCtr0 */
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#define APCI3120_SELECT_TIMER_2_LOW_WORD 0x02
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#define APCI3120_SELECT_TIMER_2_HIGH_WORD 0x03
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#define APCI3120_TIMER_CRT0 0x0D /* (ADDRESS for cCsTimerCtr0) */
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#define APCI3120_TIMER_CRT1 0x0C /* (ADDRESS for cCsTimerCtr1) */
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#define APCI3120_TIMER_VALUE 0x04 /* ADDRESS for nCsTimerWert */
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#define APCI3120_TIMER_STATUS_REGISTER 0x0D /* ADDRESS for delete timer 2 interrupt */
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#define APCI3120_RD_STATUS 0x02 /* ADDRESS */
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#define APCI3120_WR_ADDRESS 0x00 /* ADDRESS */
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#define APCI3120_ENABLE_WATCHDOG 0x20 /* $$BIT in nWrMode_Select */
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#define APCI3120_DISABLE_WATCHDOG (~APCI3120_ENABLE_WATCHDOG)
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#define APCI3120_ENABLE_TIMER_COUNTER 0x10 /* $$BIT in nWrMode_Select */
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#define APCI3120_DISABLE_TIMER_COUNTER (~APCI3120_ENABLE_TIMER_COUNTER)
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#define APCI3120_FC_TIMER 0x1000 /* bit in status register */
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#define APCI3120_ENABLE_TIMER0 0x1000
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#define APCI3120_ENABLE_TIMER1 0x2000
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#define APCI3120_ENABLE_TIMER2 0x4000
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#define APCI3120_DISABLE_TIMER0 (~APCI3120_ENABLE_TIMER0)
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#define APCI3120_DISABLE_TIMER1 (~APCI3120_ENABLE_TIMER1)
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#define APCI3120_DISABLE_TIMER2 (~APCI3120_ENABLE_TIMER2)
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#define APCI3120_TIMER2_SELECT_EOS 0xC0 /* ADDED on 20-6 */
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#define APCI3120_COUNTER 3 /* on 20-6 */
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#define APCI3120_DISABLE_ALL_TIMER (APCI3120_DISABLE_TIMER0 & APCI3120_DISABLE_TIMER1 & APCI3120_DISABLE_TIMER2) /* on 20-6 */
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#define MAX_ANALOGINPUT_CHANNELS 32
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struct str_AnalogReadInformation {
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unsigned char b_Type; /* EOC or EOS */
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unsigned char b_InterruptFlag; /* Interrupt use or not */
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unsigned int ui_ConvertTiming; /* Selection of the conversion time */
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unsigned char b_NbrOfChannel; /* Number of channel to read */
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unsigned int ui_ChannelList[MAX_ANALOGINPUT_CHANNELS]; /* Number of the channel to be read */
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unsigned int ui_RangeList[MAX_ANALOGINPUT_CHANNELS]; /* Gain of each channel */
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};
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