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net: stmmac: eic7700: add support for eth1 clock inversion variant

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The eth1 MAC exhibits silicon-inherent RX and TX timing behavior that
differs from the eth0 implementation.

At 1000Mbps, RX sampling requires clock inversion due to a fixed MAC
input skew that cannot be compensated by standard RGMII delay settings.

The TX path includes a fixed ~2ns internal delay introduced by the MAC
silicon. This delay is always present and is already accounted for in
the device tree tx-internal-delay-ps property as part of the effective
output timing.

The tx-internal-delay-ps property describes the effective delay seen at
the MAC output. Since the hardware register controls only the
programmable portion of the delay, the driver subtracts the fixed
silicon-inherent component before programming the delay register.

Use compatible-specific match data to identify the eth1 variant and
apply RX clock inversion only at 1000Mbps.

The PHY interface mode is adjusted via phy_fix_phy_mode_for_mac_delays()
to avoid double-application of RGMII delays when MAC-side delays are
already present.

Link speed dependency means RX sampling configuration is applied in the
fix_mac_speed callback after negotiation.

No behavior changes for the existing eth0 controller.

Signed-off-by: Zhi Li <lizhi2@eswincomputing.com>
Link: https://patch.msgid.link/20260707064234.1333-1-lizhi2@eswincomputing.com
Signed-off-by: Paolo Abeni <pabeni@redhat.com>
This commit is contained in:
Zhi Li
2026-07-07 14:42:32 +08:00
committed by Paolo Abeni
parent 186f38935e
commit 0cb57bdebd
1 changed files with 103 additions and 8 deletions
Download Patch File Download Diff File Expand all files Collapse all files

111
drivers/net/ethernet/stmicro/stmmac/dwmac-eic7700.c
View File

@@ -28,11 +28,15 @@
/*
* TX/RX Clock Delay Bit Masks:
* - TX Delay: bits [14:8] — TX_CLK delay (unit: 0.02ns per bit)
* - RX Delay: bits [30:24] — RX_CLK delay (unit: 0.02ns per bit)
* - TX Delay: bits [14:8] - TX_CLK delay (unit: 0.02ns per bit)
* - TX Invert : bit [15]
* - RX Delay: bits [30:24] - RX_CLK delay (unit: 0.02ns per bit)
* - RX Invert : bit [31]
*/
#define EIC7700_ETH_TX_ADJ_DELAY GENMASK(14, 8)
#define EIC7700_ETH_RX_ADJ_DELAY GENMASK(30, 24)
#define EIC7700_ETH_TX_INV_DELAY BIT(15)
#define EIC7700_ETH_RX_INV_DELAY BIT(31)
#define EIC7700_MAX_DELAY_STEPS 0x7F
#define EIC7700_DELAY_STEP_PS 20
@@ -43,7 +47,14 @@ static const char * const eic7700_clk_names[] = {
"tx", "axi", "cfg",
};
struct eic7700_dwmac_data {
bool rgmii_rx_clk_invert;
bool has_internal_tx_delay;
u32 tx_clk_inherent_skew_ps;
};
struct eic7700_qos_priv {
struct device *dev;
struct plat_stmmacenet_data *plat_dat;
struct regmap *eic7700_hsp_regmap;
u32 eth_axi_lp_ctrl_offset;
@@ -54,6 +65,7 @@ struct eic7700_qos_priv {
u32 eth_clk_dly_param;
bool has_txd_offset;
bool has_rxd_offset;
bool eth_rx_clk_inv;
};
static int eic7700_clks_config(void *priv, bool enabled)
@@ -97,9 +109,6 @@ static int eic7700_dwmac_init(struct device *dev, void *priv)
if (dwc->has_rxd_offset)
regmap_write(dwc->eic7700_hsp_regmap, dwc->eth_rxd_offset, 0);
regmap_write(dwc->eic7700_hsp_regmap, dwc->eth_clk_offset,
dwc->eth_clk_dly_param);
return 0;
}
@@ -126,8 +135,38 @@ static int eic7700_dwmac_resume(struct device *dev, void *priv)
return ret;
}
/*
* eth1 requires RX clock inversion at 1000Mbps due to silicon-inherent
* RX sampling skew at MAC input.
*
* The configuration is updated in fix_mac_speed() because the required
* sampling behavior depends on the negotiated link speed.
*/
static void eic7700_dwmac_fix_speed(void *priv, phy_interface_t interface,
int speed, unsigned int mode)
{
struct eic7700_qos_priv *dwc = (struct eic7700_qos_priv *)priv;
u32 dly_param = dwc->eth_clk_dly_param;
switch (speed) {
case SPEED_1000:
if (dwc->eth_rx_clk_inv)
dly_param |= EIC7700_ETH_RX_INV_DELAY;
break;
case SPEED_100:
case SPEED_10:
break;
default:
dev_warn(dwc->dev, "unsupported speed %u\n", speed);
return;
}
regmap_write(dwc->eic7700_hsp_regmap, dwc->eth_clk_offset, dly_param);
}
static int eic7700_dwmac_probe(struct platform_device *pdev)
{
const struct eic7700_dwmac_data *data;
struct plat_stmmacenet_data *plat_dat;
struct stmmac_resources stmmac_res;
struct eic7700_qos_priv *dwc_priv;
@@ -148,6 +187,30 @@ static int eic7700_dwmac_probe(struct platform_device *pdev)
if (!dwc_priv)
return -ENOMEM;
dwc_priv->dev = &pdev->dev;
data = device_get_match_data(&pdev->dev);
if (!data)
return dev_err_probe(&pdev->dev,
-EINVAL, "no match data found\n");
dwc_priv->eth_rx_clk_inv = data->rgmii_rx_clk_invert;
/*
* The MAC silicon unconditionally adds ~2 ns TX delay; prevent
* the PHY from also adding TX delay to avoid doubling it.
*
* DT specifies rgmii-id (TX from MAC silicon, RX from PHY);
* override to rgmii-rxid so the PHY only adds its RX delay.
*/
if (data->has_internal_tx_delay) {
plat_dat->phy_interface =
phy_fix_phy_mode_for_mac_delays(plat_dat->phy_interface,
true, false);
if (plat_dat->phy_interface == PHY_INTERFACE_MODE_NA)
return dev_err_probe(&pdev->dev, -EINVAL,
"phy interface mode is NA\n");
}
/* Read rx-internal-delay-ps and update rx_clk delay */
if (!of_property_read_u32(pdev->dev.of_node,
"rx-internal-delay-ps", &delay_ps)) {
@@ -167,7 +230,13 @@ static int eic7700_dwmac_probe(struct platform_device *pdev)
FIELD_PREP(EIC7700_ETH_RX_ADJ_DELAY, val);
}
/* Read tx-internal-delay-ps and update tx_clk delay */
/* Read tx-internal-delay-ps and update tx_clk delay.
*
* For eswin,eic7700-qos-eth-clk-inversion, the DT property describes
* the effective TX delay at the MAC output, including the inherent
* silicon delay. Subtract the fixed component to obtain the
* programmable delay value.
*/
if (!of_property_read_u32(pdev->dev.of_node,
"tx-internal-delay-ps", &delay_ps)) {
if (delay_ps % EIC7700_DELAY_STEP_PS)
@@ -175,9 +244,16 @@ static int eic7700_dwmac_probe(struct platform_device *pdev)
"tx delay must be multiple of %dps\n",
EIC7700_DELAY_STEP_PS);
if (delay_ps < data->tx_clk_inherent_skew_ps)
return dev_err_probe(&pdev->dev, -EINVAL,
"tx delay %ups below inherent skew %ups\n",
delay_ps, data->tx_clk_inherent_skew_ps);
delay_ps -= data->tx_clk_inherent_skew_ps;
if (delay_ps > EIC7700_MAX_DELAY_PS)
return dev_err_probe(&pdev->dev, -EINVAL,
"tx delay out of range\n");
"tx delay out of programmable range\n");
val = delay_ps / EIC7700_DELAY_STEP_PS;
@@ -254,12 +330,31 @@ static int eic7700_dwmac_probe(struct platform_device *pdev)
plat_dat->exit = eic7700_dwmac_exit;
plat_dat->suspend = eic7700_dwmac_suspend;
plat_dat->resume = eic7700_dwmac_resume;
plat_dat->fix_mac_speed = eic7700_dwmac_fix_speed;
return devm_stmmac_pltfr_probe(pdev, plat_dat, &stmmac_res);
}
static const struct eic7700_dwmac_data eic7700_dwmac_data = {
.rgmii_rx_clk_invert = false,
.has_internal_tx_delay = false,
.tx_clk_inherent_skew_ps = 0,
};
static const struct eic7700_dwmac_data eic7700_dwmac_data_clk_inversion = {
.rgmii_rx_clk_invert = true,
.has_internal_tx_delay = true,
.tx_clk_inherent_skew_ps = 2000,
};
static const struct of_device_id eic7700_dwmac_match[] = {
{ .compatible = "eswin,eic7700-qos-eth" },
{ .compatible = "eswin,eic7700-qos-eth",
.data = &eic7700_dwmac_data,
},
{
.compatible = "eswin,eic7700-qos-eth-clk-inversion",
.data = &eic7700_dwmac_data_clk_inversion,
},
{ }
};
MODULE_DEVICE_TABLE(of, eic7700_dwmac_match);