mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
synced 2026-05-03 19:26:01 -04:00
Merge branch 'bnxt_en-fixes'
Michael Chan says: ==================== bnxt_en: Misc. bug fixes This series fixes a bug in the driver initialization path, MSIX setup sequencing issue in the FW error and AER paths, a missing skb_mark_for_recycle() in the VLAN error path, some ethtool coredump fixes, an ethtool selftest fix, and an ethtool register dump byte order fix. ==================== Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
@@ -2015,6 +2015,7 @@ static struct sk_buff *bnxt_rx_vlan(struct sk_buff *skb, u8 cmp_type,
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}
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return skb;
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vlan_err:
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skb_mark_for_recycle(skb);
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dev_kfree_skb(skb);
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return NULL;
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}
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@@ -11602,6 +11603,9 @@ static void bnxt_init_napi(struct bnxt *bp)
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poll_fn = bnxt_poll_p5;
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else if (BNXT_CHIP_TYPE_NITRO_A0(bp))
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cp_nr_rings--;
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set_bit(BNXT_STATE_NAPI_DISABLED, &bp->state);
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for (i = 0; i < cp_nr_rings; i++) {
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bnapi = bp->bnapi[i];
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netif_napi_add_config_locked(bp->dev, &bnapi->napi, poll_fn,
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@@ -12321,12 +12325,15 @@ static int bnxt_hwrm_if_change(struct bnxt *bp, bool up)
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{
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struct hwrm_func_drv_if_change_output *resp;
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struct hwrm_func_drv_if_change_input *req;
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bool fw_reset = !bp->irq_tbl;
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bool resc_reinit = false;
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bool caps_change = false;
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int rc, retry = 0;
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bool fw_reset;
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u32 flags = 0;
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fw_reset = (bp->fw_reset_state == BNXT_FW_RESET_STATE_ABORT);
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bp->fw_reset_state = 0;
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if (!(bp->fw_cap & BNXT_FW_CAP_IF_CHANGE))
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return 0;
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@@ -12395,13 +12402,8 @@ static int bnxt_hwrm_if_change(struct bnxt *bp, bool up)
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set_bit(BNXT_STATE_ABORT_ERR, &bp->state);
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return rc;
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}
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/* IRQ will be initialized later in bnxt_request_irq()*/
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bnxt_clear_int_mode(bp);
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rc = bnxt_init_int_mode(bp);
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if (rc) {
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clear_bit(BNXT_STATE_FW_RESET_DET, &bp->state);
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netdev_err(bp->dev, "init int mode failed\n");
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return rc;
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}
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}
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rc = bnxt_cancel_reservations(bp, fw_reset);
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}
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@@ -14834,7 +14836,7 @@ static void bnxt_fw_reset_abort(struct bnxt *bp, int rc)
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clear_bit(BNXT_STATE_IN_FW_RESET, &bp->state);
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if (bp->fw_reset_state != BNXT_FW_RESET_STATE_POLL_VF)
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bnxt_dl_health_fw_status_update(bp, false);
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bp->fw_reset_state = 0;
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bp->fw_reset_state = BNXT_FW_RESET_STATE_ABORT;
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netif_close(bp->dev);
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}
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@@ -16932,10 +16934,9 @@ static pci_ers_result_t bnxt_io_slot_reset(struct pci_dev *pdev)
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if (!err)
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result = PCI_ERS_RESULT_RECOVERED;
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/* IRQ will be initialized later in bnxt_io_resume */
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bnxt_ulp_irq_stop(bp);
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bnxt_clear_int_mode(bp);
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err = bnxt_init_int_mode(bp);
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bnxt_ulp_irq_restart(bp, err);
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}
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reset_exit:
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@@ -16964,10 +16965,13 @@ static void bnxt_io_resume(struct pci_dev *pdev)
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err = bnxt_hwrm_func_qcaps(bp);
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if (!err) {
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if (netif_running(netdev))
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if (netif_running(netdev)) {
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err = bnxt_open(netdev);
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else
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} else {
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err = bnxt_reserve_rings(bp, true);
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if (!err)
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err = bnxt_init_int_mode(bp);
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}
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}
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if (!err)
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@@ -2614,6 +2614,7 @@ struct bnxt {
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#define BNXT_FW_RESET_STATE_POLL_FW 4
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#define BNXT_FW_RESET_STATE_OPENING 5
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#define BNXT_FW_RESET_STATE_POLL_FW_DOWN 6
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#define BNXT_FW_RESET_STATE_ABORT 7
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u16 fw_reset_min_dsecs;
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#define BNXT_DFLT_FW_RST_MIN_DSECS 20
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@@ -110,20 +110,30 @@ static int bnxt_hwrm_dbg_dma_data(struct bnxt *bp, void *msg,
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}
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}
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if (info->dest_buf) {
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if ((info->seg_start + off + len) <=
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BNXT_COREDUMP_BUF_LEN(info->buf_len)) {
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memcpy(info->dest_buf + off, dma_buf, len);
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} else {
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rc = -ENOBUFS;
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break;
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}
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}
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if (cmn_req->req_type ==
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cpu_to_le16(HWRM_DBG_COREDUMP_RETRIEVE))
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info->dest_buf_size += len;
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if (info->dest_buf) {
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if ((info->seg_start + off + len) <=
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BNXT_COREDUMP_BUF_LEN(info->buf_len)) {
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u16 copylen = min_t(u16, len,
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info->dest_buf_size - off);
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memcpy(info->dest_buf + off, dma_buf, copylen);
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if (copylen < len)
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break;
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} else {
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rc = -ENOBUFS;
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if (cmn_req->req_type ==
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cpu_to_le16(HWRM_DBG_COREDUMP_LIST)) {
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kfree(info->dest_buf);
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info->dest_buf = NULL;
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}
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break;
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}
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}
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if (!(cmn_resp->flags & HWRM_DBG_CMN_FLAGS_MORE))
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break;
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@@ -2062,6 +2062,17 @@ static int bnxt_get_regs_len(struct net_device *dev)
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return reg_len;
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}
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#define BNXT_PCIE_32B_ENTRY(start, end) \
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{ offsetof(struct pcie_ctx_hw_stats, start), \
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offsetof(struct pcie_ctx_hw_stats, end) }
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static const struct {
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u16 start;
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u16 end;
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} bnxt_pcie_32b_entries[] = {
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BNXT_PCIE_32B_ENTRY(pcie_ltssm_histogram[0], pcie_ltssm_histogram[3]),
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};
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static void bnxt_get_regs(struct net_device *dev, struct ethtool_regs *regs,
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void *_p)
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{
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@@ -2094,12 +2105,27 @@ static void bnxt_get_regs(struct net_device *dev, struct ethtool_regs *regs,
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req->pcie_stat_host_addr = cpu_to_le64(hw_pcie_stats_addr);
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rc = hwrm_req_send(bp, req);
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if (!rc) {
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__le64 *src = (__le64 *)hw_pcie_stats;
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u64 *dst = (u64 *)(_p + BNXT_PXP_REG_LEN);
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int i;
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u8 *dst = (u8 *)(_p + BNXT_PXP_REG_LEN);
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u8 *src = (u8 *)hw_pcie_stats;
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int i, j;
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for (i = 0; i < sizeof(*hw_pcie_stats) / sizeof(__le64); i++)
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dst[i] = le64_to_cpu(src[i]);
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for (i = 0, j = 0; i < sizeof(*hw_pcie_stats); ) {
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if (i >= bnxt_pcie_32b_entries[j].start &&
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i <= bnxt_pcie_32b_entries[j].end) {
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u32 *dst32 = (u32 *)(dst + i);
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*dst32 = le32_to_cpu(*(__le32 *)(src + i));
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i += 4;
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if (i > bnxt_pcie_32b_entries[j].end &&
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j < ARRAY_SIZE(bnxt_pcie_32b_entries) - 1)
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j++;
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} else {
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u64 *dst64 = (u64 *)(dst + i);
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*dst64 = le64_to_cpu(*(__le64 *)(src + i));
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i += 8;
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}
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}
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}
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hwrm_req_drop(bp, req);
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}
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@@ -4991,6 +5017,7 @@ static void bnxt_self_test(struct net_device *dev, struct ethtool_test *etest,
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if (!bp->num_tests || !BNXT_PF(bp))
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return;
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memset(buf, 0, sizeof(u64) * bp->num_tests);
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if (etest->flags & ETH_TEST_FL_OFFLINE &&
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bnxt_ulp_registered(bp->edev)) {
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etest->flags |= ETH_TEST_FL_FAILED;
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@@ -4998,7 +5025,6 @@ static void bnxt_self_test(struct net_device *dev, struct ethtool_test *etest,
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return;
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}
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memset(buf, 0, sizeof(u64) * bp->num_tests);
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if (!netif_running(dev)) {
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etest->flags |= ETH_TEST_FL_FAILED;
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return;
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