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arm64: dts: qcom: x1e80100: Add missing TCSR ref clock to the DP PHYs

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The DP PHYs on X1E80100 need the ref clock which is provided by the
TCSR CC.

The current X Elite devices supported upstream work fine without this
clock, because the boot firmware leaves this clock enabled. But we should
not rely on that. Also, even though this change breaks the ABI, it is
needed in order to make the driver disables this clock along with the
other ones, for a proper bring-down of the entire PHY.

So lets attach it to each of the DP PHYs in order to do that.

Cc: stable@vger.kernel.org # v6.9
Fixes: 1940c25eaa ("arm64: dts: qcom: x1e80100: Add display nodes")
Reviewed-by: Bjorn Andersson <andersson@kernel.org>
Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
Link: https://lore.kernel.org/r/20251224-phy-qcom-edp-add-missing-refclk-v5-3-3f45d349b5ac@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
This commit is contained in:
Abel Vesa
2025-12-24 12:53:29 +02:00
committed by Bjorn Andersson
parent 09d87fdd83
commit 0907cab01f
1 changed files with 8 additions and 4 deletions
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12
arch/arm64/boot/dts/qcom/hamoa.dtsi
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@@ -5929,9 +5929,11 @@ mdss_dp2_phy: phy@aec2a00 {
<0 0x0aec2000 0 0x1c8>;
clocks = <&dispcc DISP_CC_MDSS_DPTX2_AUX_CLK>,
<&dispcc DISP_CC_MDSS_AHB_CLK>;
<&dispcc DISP_CC_MDSS_AHB_CLK>,
<&tcsr TCSR_EDP_CLKREF_EN>;
clock-names = "aux",
"cfg_ahb";
"cfg_ahb",
"ref";
power-domains = <&rpmhpd RPMHPD_MX>;
@@ -5949,9 +5951,11 @@ mdss_dp3_phy: phy@aec5a00 {
<0 0x0aec5000 0 0x1c8>;
clocks = <&dispcc DISP_CC_MDSS_DPTX3_AUX_CLK>,
<&dispcc DISP_CC_MDSS_AHB_CLK>;
<&dispcc DISP_CC_MDSS_AHB_CLK>,
<&tcsr TCSR_EDP_CLKREF_EN>;
clock-names = "aux",
"cfg_ahb";
"cfg_ahb",
"ref";
power-domains = <&rpmhpd RPMHPD_MX>;