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net: macb: unify variable naming convention in at91ether functions

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Follow MACB naming convention throughout on two aspects:
 - Always name `struct macb *bp` rather than `lp`.
 - Always name `struct macb_queue *queue` rather than `q`.

The latter is to reserve `q` for queue indexes.

Acked-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: Nicolai Buchwitz <nb@tipi-net.de>
Signed-off-by: Théo Lebrun <theo.lebrun@bootlin.com>
Link: https://patch.msgid.link/20260812-macb-context-v9-3-7ddbf5f715e0@bootlin.com
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
This commit is contained in:
Théo Lebrun
2026-08-12 10:03:17 +02:00
committed by Jakub Kicinski
parent 07362f68e6
commit 075663a6ce
1 changed files with 91 additions and 85 deletions
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176
drivers/net/ethernet/cadence/macb_main.c
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@@ -4965,71 +4965,72 @@ static const struct macb_usrio_config at91_default_usrio = {
static struct sifive_fu540_macb_mgmt *mgmt;
static int at91ether_alloc_coherent(struct macb *lp)
static int at91ether_alloc_coherent(struct macb *bp)
{
struct macb_queue *q = &lp->queues[0];
struct macb_queue *queue = &bp->queues[0];
q->rx_ring = dma_alloc_coherent(&lp->pdev->dev,
(AT91ETHER_MAX_RX_DESCR *
macb_dma_desc_get_size(lp)),
&q->rx_ring_dma, GFP_KERNEL);
if (!q->rx_ring)
queue->rx_ring = dma_alloc_coherent(&bp->pdev->dev,
(AT91ETHER_MAX_RX_DESCR *
macb_dma_desc_get_size(bp)),
&queue->rx_ring_dma, GFP_KERNEL);
if (!queue->rx_ring)
return -ENOMEM;
q->rx_buffers = dma_alloc_coherent(&lp->pdev->dev,
AT91ETHER_MAX_RX_DESCR *
AT91ETHER_MAX_RBUFF_SZ,
&q->rx_buffers_dma, GFP_KERNEL);
if (!q->rx_buffers) {
dma_free_coherent(&lp->pdev->dev,
queue->rx_buffers = dma_alloc_coherent(&bp->pdev->dev,
AT91ETHER_MAX_RX_DESCR *
AT91ETHER_MAX_RBUFF_SZ,
&queue->rx_buffers_dma,
GFP_KERNEL);
if (!queue->rx_buffers) {
dma_free_coherent(&bp->pdev->dev,
AT91ETHER_MAX_RX_DESCR *
macb_dma_desc_get_size(lp),
q->rx_ring, q->rx_ring_dma);
q->rx_ring = NULL;
macb_dma_desc_get_size(bp),
queue->rx_ring, queue->rx_ring_dma);
queue->rx_ring = NULL;
return -ENOMEM;
}
return 0;
}
static void at91ether_free_coherent(struct macb *lp)
static void at91ether_free_coherent(struct macb *bp)
{
struct macb_queue *q = &lp->queues[0];
struct macb_queue *queue = &bp->queues[0];
if (q->rx_ring) {
dma_free_coherent(&lp->pdev->dev,
if (queue->rx_ring) {
dma_free_coherent(&bp->pdev->dev,
AT91ETHER_MAX_RX_DESCR *
macb_dma_desc_get_size(lp),
q->rx_ring, q->rx_ring_dma);
q->rx_ring = NULL;
macb_dma_desc_get_size(bp),
queue->rx_ring, queue->rx_ring_dma);
queue->rx_ring = NULL;
}
if (q->rx_buffers) {
dma_free_coherent(&lp->pdev->dev,
if (queue->rx_buffers) {
dma_free_coherent(&bp->pdev->dev,
AT91ETHER_MAX_RX_DESCR *
AT91ETHER_MAX_RBUFF_SZ,
q->rx_buffers, q->rx_buffers_dma);
q->rx_buffers = NULL;
queue->rx_buffers, queue->rx_buffers_dma);
queue->rx_buffers = NULL;
}
}
/* Initialize and start the Receiver and Transmit subsystems */
static int at91ether_start(struct macb *lp)
static int at91ether_start(struct macb *bp)
{
struct macb_queue *q = &lp->queues[0];
struct macb_queue *queue = &bp->queues[0];
struct macb_dma_desc *desc;
dma_addr_t addr;
u32 ctl;
int i, ret;
ret = at91ether_alloc_coherent(lp);
ret = at91ether_alloc_coherent(bp);
if (ret)
return ret;
addr = q->rx_buffers_dma;
addr = queue->rx_buffers_dma;
for (i = 0; i < AT91ETHER_MAX_RX_DESCR; i++) {
desc = macb_rx_desc(q, i);
macb_set_addr(lp, desc, addr);
desc = macb_rx_desc(queue, i);
macb_set_addr(bp, desc, addr);
desc->ctrl = 0;
addr += AT91ETHER_MAX_RBUFF_SZ;
}
@@ -5038,17 +5039,17 @@ static int at91ether_start(struct macb *lp)
desc->addr |= MACB_BIT(RX_WRAP);
/* Reset buffer index */
q->rx_tail = 0;
queue->rx_tail = 0;
/* Program address of descriptor list in Rx Buffer Queue register */
macb_writel(lp, RBQP, q->rx_ring_dma);
macb_writel(bp, RBQP, queue->rx_ring_dma);
/* Enable Receive and Transmit */
ctl = macb_readl(lp, NCR);
macb_writel(lp, NCR, ctl | MACB_BIT(RE) | MACB_BIT(TE));
ctl = macb_readl(bp, NCR);
macb_writel(bp, NCR, ctl | MACB_BIT(RE) | MACB_BIT(TE));
/* Enable MAC interrupts */
macb_writel(lp, IER, MACB_BIT(RCOMP) |
macb_writel(bp, IER, MACB_BIT(RCOMP) |
MACB_BIT(RXUBR) |
MACB_BIT(ISR_TUND) |
MACB_BIT(ISR_RLE) |
@@ -5059,12 +5060,12 @@ static int at91ether_start(struct macb *lp)
return 0;
}
static void at91ether_stop(struct macb *lp)
static void at91ether_stop(struct macb *bp)
{
u32 ctl;
/* Disable MAC interrupts */
macb_writel(lp, IDR, MACB_BIT(RCOMP) |
macb_writel(bp, IDR, MACB_BIT(RCOMP) |
MACB_BIT(RXUBR) |
MACB_BIT(ISR_TUND) |
MACB_BIT(ISR_RLE) |
@@ -5073,35 +5074,35 @@ static void at91ether_stop(struct macb *lp)
MACB_BIT(HRESP));
/* Disable Receiver and Transmitter */
ctl = macb_readl(lp, NCR);
macb_writel(lp, NCR, ctl & ~(MACB_BIT(TE) | MACB_BIT(RE)));
ctl = macb_readl(bp, NCR);
macb_writel(bp, NCR, ctl & ~(MACB_BIT(TE) | MACB_BIT(RE)));
/* Free resources. */
at91ether_free_coherent(lp);
at91ether_free_coherent(bp);
}
/* Open the ethernet interface */
static int at91ether_open(struct net_device *netdev)
{
struct macb *lp = netdev_priv(netdev);
struct macb *bp = netdev_priv(netdev);
u32 ctl;
int ret;
ret = pm_runtime_resume_and_get(&lp->pdev->dev);
ret = pm_runtime_resume_and_get(&bp->pdev->dev);
if (ret < 0)
return ret;
/* Clear internal statistics */
ctl = macb_readl(lp, NCR);
macb_writel(lp, NCR, ctl | MACB_BIT(CLRSTAT));
ctl = macb_readl(bp, NCR);
macb_writel(bp, NCR, ctl | MACB_BIT(CLRSTAT));
macb_set_hwaddr(lp);
macb_set_hwaddr(bp);
ret = at91ether_start(lp);
ret = at91ether_start(bp);
if (ret)
goto pm_exit;
ret = macb_phylink_connect(lp);
ret = macb_phylink_connect(bp);
if (ret)
goto stop;
@@ -5110,25 +5111,25 @@ static int at91ether_open(struct net_device *netdev)
return 0;
stop:
at91ether_stop(lp);
at91ether_stop(bp);
pm_exit:
pm_runtime_put_sync(&lp->pdev->dev);
pm_runtime_put_sync(&bp->pdev->dev);
return ret;
}
/* Close the interface */
static int at91ether_close(struct net_device *netdev)
{
struct macb *lp = netdev_priv(netdev);
struct macb *bp = netdev_priv(netdev);
netif_stop_queue(netdev);
phylink_stop(lp->phylink);
phylink_disconnect_phy(lp->phylink);
phylink_stop(bp->phylink);
phylink_disconnect_phy(bp->phylink);
at91ether_stop(lp);
at91ether_stop(bp);
pm_runtime_put(&lp->pdev->dev);
pm_runtime_put(&bp->pdev->dev);
return 0;
}
@@ -5137,19 +5138,21 @@ static int at91ether_close(struct net_device *netdev)
static netdev_tx_t at91ether_start_xmit(struct sk_buff *skb,
struct net_device *netdev)
{
struct macb *lp = netdev_priv(netdev);
struct macb *bp = netdev_priv(netdev);
struct device *dev = &bp->pdev->dev;
if (macb_readl(lp, TSR) & MACB_BIT(RM9200_BNQ)) {
if (macb_readl(bp, TSR) & MACB_BIT(RM9200_BNQ)) {
int desc = 0;
netif_stop_queue(netdev);
/* Store packet information (to free when Tx completed) */
lp->rm9200_txq[desc].skb = skb;
lp->rm9200_txq[desc].size = skb->len;
lp->rm9200_txq[desc].mapping = dma_map_single(&lp->pdev->dev, skb->data,
skb->len, DMA_TO_DEVICE);
if (dma_mapping_error(&lp->pdev->dev, lp->rm9200_txq[desc].mapping)) {
bp->rm9200_txq[desc].skb = skb;
bp->rm9200_txq[desc].size = skb->len;
bp->rm9200_txq[desc].mapping = dma_map_single(dev, skb->data,
skb->len,
DMA_TO_DEVICE);
if (dma_mapping_error(dev, bp->rm9200_txq[desc].mapping)) {
dev_kfree_skb_any(skb);
netdev->stats.tx_dropped++;
netdev_err(netdev, "%s: DMA mapping error\n", __func__);
@@ -5157,9 +5160,9 @@ static netdev_tx_t at91ether_start_xmit(struct sk_buff *skb,
}
/* Set address of the data in the Transmit Address register */
macb_writel(lp, TAR, lp->rm9200_txq[desc].mapping);
macb_writel(bp, TAR, bp->rm9200_txq[desc].mapping);
/* Set length of the packet in the Transmit Control register */
macb_writel(lp, TCR, skb->len);
macb_writel(bp, TCR, skb->len);
} else {
netdev_err(netdev, "%s called, but device is busy!\n",
@@ -5175,16 +5178,17 @@ static netdev_tx_t at91ether_start_xmit(struct sk_buff *skb,
*/
static void at91ether_rx(struct net_device *netdev)
{
struct macb *lp = netdev_priv(netdev);
struct macb_queue *q = &lp->queues[0];
struct macb *bp = netdev_priv(netdev);
struct macb_queue *queue = &bp->queues[0];
struct macb_dma_desc *desc;
unsigned char *p_recv;
struct sk_buff *skb;
unsigned int pktlen;
desc = macb_rx_desc(q, q->rx_tail);
desc = macb_rx_desc(queue, queue->rx_tail);
while (desc->addr & MACB_BIT(RX_USED)) {
p_recv = q->rx_buffers + q->rx_tail * AT91ETHER_MAX_RBUFF_SZ;
p_recv = queue->rx_buffers +
queue->rx_tail * AT91ETHER_MAX_RBUFF_SZ;
pktlen = MACB_BF(RX_FRMLEN, desc->ctrl);
skb = netdev_alloc_skb(netdev, pktlen + 2);
if (skb) {
@@ -5206,12 +5210,12 @@ static void at91ether_rx(struct net_device *netdev)
desc->addr &= ~MACB_BIT(RX_USED);
/* wrap after last buffer */
if (q->rx_tail == AT91ETHER_MAX_RX_DESCR - 1)
q->rx_tail = 0;
if (queue->rx_tail == AT91ETHER_MAX_RX_DESCR - 1)
queue->rx_tail = 0;
else
q->rx_tail++;
queue->rx_tail++;
desc = macb_rx_desc(q, q->rx_tail);
desc = macb_rx_desc(queue, queue->rx_tail);
}
}
@@ -5219,14 +5223,14 @@ static void at91ether_rx(struct net_device *netdev)
static irqreturn_t at91ether_interrupt(int irq, void *dev_id)
{
struct net_device *netdev = dev_id;
struct macb *lp = netdev_priv(netdev);
struct macb *bp = netdev_priv(netdev);
u32 intstatus, ctl;
unsigned int desc;
/* MAC Interrupt Status register indicates what interrupts are pending.
* It is automatically cleared once read.
*/
intstatus = macb_readl(lp, ISR);
intstatus = macb_readl(bp, ISR);
/* Receive complete */
if (intstatus & MACB_BIT(RCOMP))
@@ -5239,23 +5243,25 @@ static irqreturn_t at91ether_interrupt(int irq, void *dev_id)
netdev->stats.tx_errors++;
desc = 0;
if (lp->rm9200_txq[desc].skb) {
dev_consume_skb_irq(lp->rm9200_txq[desc].skb);
lp->rm9200_txq[desc].skb = NULL;
dma_unmap_single(&lp->pdev->dev, lp->rm9200_txq[desc].mapping,
lp->rm9200_txq[desc].size, DMA_TO_DEVICE);
if (bp->rm9200_txq[desc].skb) {
dev_consume_skb_irq(bp->rm9200_txq[desc].skb);
bp->rm9200_txq[desc].skb = NULL;
dma_unmap_single(&bp->pdev->dev,
bp->rm9200_txq[desc].mapping,
bp->rm9200_txq[desc].size,
DMA_TO_DEVICE);
netdev->stats.tx_packets++;
netdev->stats.tx_bytes += lp->rm9200_txq[desc].size;
netdev->stats.tx_bytes += bp->rm9200_txq[desc].size;
}
netif_wake_queue(netdev);
}
/* Work-around for EMAC Errata section 41.3.1 */
if (intstatus & MACB_BIT(RXUBR)) {
ctl = macb_readl(lp, NCR);
macb_writel(lp, NCR, ctl & ~MACB_BIT(RE));
ctl = macb_readl(bp, NCR);
macb_writel(bp, NCR, ctl & ~MACB_BIT(RE));
wmb();
macb_writel(lp, NCR, ctl | MACB_BIT(RE));
macb_writel(bp, NCR, ctl | MACB_BIT(RE));
}
if (intstatus & MACB_BIT(ISR_ROVR))