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arm64: dts: qcom: x1e80100: Add cpucp mailbox and sram nodes

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Add the cpucp mailbox and sram nodes required by SCMI perf protocol
on X1E80100 SoCs.

Signed-off-by: Sibi Sankar <quic_sibis@quicinc.com>
Link: https://lore.kernel.org/r/20241030130840.2890904-2-quic_sibis@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
This commit is contained in:
Sibi Sankar
2024-10-30 18:38:39 +05:30
committed by Bjorn Andersson
parent 9c6ee9a760
commit 06e3c7ec80
1 changed files with 26 additions and 0 deletions
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26
arch/arm64/boot/dts/qcom/x1e80100.dtsi
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@@ -7980,6 +7980,13 @@ gic_its: msi-controller@17040000 {
};
};
cpucp_mbox: mailbox@17430000 {
compatible = "qcom,x1e80100-cpucp-mbox";
reg = <0 0x17430000 0 0x10000>, <0 0x18830000 0 0x10000>;
interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
#mbox-cells = <1>;
};
apps_rsc: rsc@17500000 {
compatible = "qcom,rpmh-rsc";
reg = <0 0x17500000 0 0x10000>,
@@ -8163,6 +8170,25 @@ frame@1780d000 {
};
};
sram: sram@18b4e000 {
compatible = "mmio-sram";
reg = <0x0 0x18b4e000 0x0 0x400>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x0 0x18b4e000 0x400>;
cpu_scp_lpri0: scp-sram-section@0 {
compatible = "arm,scmi-shmem";
reg = <0x0 0x200>;
};
cpu_scp_lpri1: scp-sram-section@200 {
compatible = "arm,scmi-shmem";
reg = <0x200 0x200>;
};
};
sbsa_watchdog: watchdog@1c840000 {
compatible = "arm,sbsa-gwdt";
reg = <0 0x1c840000 0 0x1000>,