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drm/i915/mtl: Don't mask off CCS according to DSS fusing

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Unlike the Xe_HP platforms, MTL only has a single CCS engine; the
quad-based engine masking logic does not apply to this platform (or
presumably any future platforms that only have 0 or 1 CCS).

Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
Reviewed-by: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220818234202.451742-5-radhakrishna.sripada@intel.com
This commit is contained in:
Matt Roper
2022-08-18 16:41:45 -07:00
committed by Radhakrishna Sripada
parent da30390b93
commit 068a0f5c82
1 changed files with 1 additions and 1 deletions
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2
drivers/gpu/drm/i915/gt/intel_engine_cs.c
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@@ -672,7 +672,7 @@ static void engine_mask_apply_compute_fuses(struct intel_gt *gt)
unsigned long ccs_mask;
unsigned int i;
if (GRAPHICS_VER_FULL(i915) < IP_VER(12, 50))
if (hweight32(CCS_MASK(gt)) <= 1)
return;
ccs_mask = intel_slicemask_from_xehp_dssmask(info->sseu.compute_subslice_mask,