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Merge tag 'amlogic-drivers-for-v6.3' of https://git.kernel.org/pub/scm/linux/kernel/git/amlogic/linux into soc/drivers
Amlogic Drivers changes for v6.3: - Merge of immutable bindings branch with Reset & power domain binding - Addition of NNA power domain for A311D SoC - meson_sm.txt conversionto dt-schema - mark amlogic,meson-gx-pwrc bindings as deprecated - fix of meson_sm driver by using NULL instead of 0 * tag 'amlogic-drivers-for-v6.3' of https://git.kernel.org/pub/scm/linux/kernel/git/amlogic/linux: firmware: meson_sm: stop using 0 as NULL pointer dt-bindings: power: amlogic,meson-gx-pwrc: mark bindings as deprecated dt-bindings: firmware: convert meson_sm.txt to dt-schema soc: amlogic: meson-pwrc: Add NNA power domain for A311D dt-bindings: power: Add G12A NNA power domain dt-bindings: reset: meson-g12a: Add missing NNA reset Link: https://lore.kernel.org/r/ec9552d8-96df-a677-ab94-9723f5c30f1c@linaro.org Signed-off-by: Arnd Bergmann <arnd@arndb.de>
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@@ -0,0 +1,39 @@
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/firmware/amlogic,meson-gxbb-sm.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Amlogic Secure Monitor (SM)
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description:
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In the Amlogic SoCs the Secure Monitor code is used to provide access to the
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NVMEM, enable JTAG, set USB boot, etc...
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maintainers:
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- Neil Armstrong <neil.armstrong@linaro.org>
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properties:
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compatible:
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oneOf:
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- const: amlogic,meson-gxbb-sm
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- items:
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- const: amlogic,meson-gx-sm
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- const: amlogic,meson-gxbb-sm
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power-controller:
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type: object
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$ref: /schemas/power/amlogic,meson-sec-pwrc.yaml#
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required:
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- compatible
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additionalProperties: false
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examples:
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- |
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firmware {
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secure-monitor {
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compatible = "amlogic,meson-gxbb-sm";
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};
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};
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@@ -1,15 +0,0 @@
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* Amlogic Secure Monitor
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In the Amlogic SoCs the Secure Monitor code is used to provide access to the
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NVMEM, enable JTAG, set USB boot, etc...
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Required properties for the secure monitor node:
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- compatible: Should be "amlogic,meson-gxbb-sm"
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Example:
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firmware {
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sm: secure-monitor {
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compatible = "amlogic,meson-gxbb-sm";
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};
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};
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@@ -1,5 +1,5 @@
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Amlogic Meson Power Controller
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==============================
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Amlogic Meson Power Controller (deprecated)
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===========================================
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The Amlogic Meson SoCs embeds an internal Power domain controller.
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@@ -82,7 +82,7 @@ static void __iomem *meson_sm_map_shmem(u32 cmd_shmem, unsigned int size)
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sm_phy_base = __meson_sm_call(cmd_shmem, 0, 0, 0, 0, 0);
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if (!sm_phy_base)
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return 0;
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return NULL;
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return ioremap_cache(sm_phy_base, size);
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}
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@@ -46,6 +46,9 @@
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#define HHI_NANOQ_MEM_PD_REG1 (0x47 << 2)
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#define HHI_VPU_MEM_PD_REG2 (0x4d << 2)
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#define G12A_HHI_NANOQ_MEM_PD_REG0 (0x43 << 2)
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#define G12A_HHI_NANOQ_MEM_PD_REG1 (0x44 << 2)
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struct meson_ee_pwrc;
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struct meson_ee_pwrc_domain;
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@@ -106,6 +109,13 @@ static struct meson_ee_pwrc_top_domain sm1_pwrc_usb = SM1_EE_PD(17);
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static struct meson_ee_pwrc_top_domain sm1_pwrc_pci = SM1_EE_PD(18);
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static struct meson_ee_pwrc_top_domain sm1_pwrc_ge2d = SM1_EE_PD(19);
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static struct meson_ee_pwrc_top_domain g12a_pwrc_nna = {
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.sleep_reg = GX_AO_RTI_GEN_PWR_SLEEP0,
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.sleep_mask = BIT(16) | BIT(17),
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.iso_reg = GX_AO_RTI_GEN_PWR_ISO0,
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.iso_mask = BIT(16) | BIT(17),
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};
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/* Memory PD Domains */
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#define VPU_MEMPD(__reg) \
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@@ -217,6 +227,11 @@ static struct meson_ee_pwrc_mem_domain sm1_pwrc_mem_audio[] = {
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{ HHI_AUDIO_MEM_PD_REG0, GENMASK(27, 26) },
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};
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static struct meson_ee_pwrc_mem_domain g12a_pwrc_mem_nna[] = {
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{ G12A_HHI_NANOQ_MEM_PD_REG0, GENMASK(31, 0) },
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{ G12A_HHI_NANOQ_MEM_PD_REG1, GENMASK(23, 0) },
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};
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#define VPU_PD(__name, __top_pd, __mem, __is_pwr_off, __resets, __clks) \
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{ \
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.name = __name, \
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@@ -253,6 +268,8 @@ static struct meson_ee_pwrc_domain_desc g12a_pwrc_domains[] = {
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[PWRC_G12A_VPU_ID] = VPU_PD("VPU", &gx_pwrc_vpu, g12a_pwrc_mem_vpu,
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pwrc_ee_is_powered_off, 11, 2),
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[PWRC_G12A_ETH_ID] = MEM_PD("ETH", meson_pwrc_mem_eth),
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[PWRC_G12A_NNA_ID] = TOP_PD("NNA", &g12a_pwrc_nna, g12a_pwrc_mem_nna,
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pwrc_ee_is_powered_off),
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};
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static struct meson_ee_pwrc_domain_desc gxbb_pwrc_domains[] = {
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@@ -9,5 +9,6 @@
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#define PWRC_G12A_VPU_ID 0
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#define PWRC_G12A_ETH_ID 1
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#define PWRC_G12A_NNA_ID 2
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#endif
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@@ -69,7 +69,9 @@
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#define RESET_PARSER_FETCH 72
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#define RESET_CTL 73
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#define RESET_PARSER_TOP 74
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/* 75-77 */
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/* 75 */
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#define RESET_NNA 76
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/* 77 */
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#define RESET_DVALIN 78
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#define RESET_HDMITX 79
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/* 80-95 */
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