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irqchip/gic-v3-its: Fix access width for gicr_syncr

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GICR_SYNCR is a 32bit register, so it is better to access it with
32bit access width, though we have not seen any real problem.

Signed-off-by: Heyi Guo <guoheyi@huawei.com>
Signed-off-by: Marc Zyngier <maz@kernel.org>
Link: https://lore.kernel.org/r/20200225090023.28020-1-guoheyi@huawei.com
This commit is contained in:
Heyi Guo
2020-02-25 17:00:23 +08:00
committed by Marc Zyngier
parent 47beed513a
commit 04d80dbe85
1 changed files with 1 additions and 1 deletions
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2
drivers/irqchip/irq-gic-v3-its.c
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@@ -1321,7 +1321,7 @@ static void lpi_write_config(struct irq_data *d, u8 clr, u8 set)
static void wait_for_syncr(void __iomem *rdbase)
{
while (gic_read_lpir(rdbase + GICR_SYNCR) & 1)
while (readl_relaxed(rdbase + GICR_SYNCR) & 1)
cpu_relax();
}