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Merge branch 'devlink-mlx5-add-new-parameters-for-link-management-and-sriov-eswitch-configurations'

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Saeed Mahameed says:

====================
devlink, mlx5: Add new parameters for link management and SRIOV/eSwitch configurations [part]

This patch series introduces several devlink parameters improving device
configuration capabilities, link management, and SRIOV/eSwitch, by adding
NV config boot time parameters.

Implement the following parameters:

   a) total_vfs Parameter:
   -----------------------

Adds support for managing the number of VFs (total_vfs) and enabling
SR-IOV (enable_sriov for mlx5) through devlink. These additions enhance
user control over virtualization features directly from standard kernel
interfaces without relying on additional external tools. total_vfs
functionality is critical for environments that require flexible num VF
configuration.

   b) CQE Compression Type:
   ------------------------

Introduces a new devlink parameter, cqe_compress_type, to configure the
rate of CQE compression based on PCIe bus conditions. This setting
provides a balance between compression efficiency and overall NIC
performance under different traffic loads.
====================

Link: https://patch.msgid.link/20250907012953.301746-1-saeed@kernel.org
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
This commit is contained in:
Jakub Kicinski
2025-09-09 19:14:31 -07:00
parent b90c7ca4f9 a4c49611cf
commit 04d1ff1d75
10 changed files with 658 additions and 4 deletions
Download Patch File Download Diff File Expand all files Collapse all files

5
Documentation/networking/devlink/devlink-params.rst
View File

@@ -143,3 +143,8 @@ own name.
* - ``clock_id``
- u64
- Clock ID used by the device for registering DPLL devices and pins.
* - ``total_vfs``
- u32
- The max number of Virtual Functions (VFs) exposed by the PF.
after reboot/pci reset, 'sriov_totalvfs' entry under the device's sysfs
directory will report this value.

46
Documentation/networking/devlink/mlx5.rst
View File

@@ -15,23 +15,53 @@ Parameters
* - Name
- Mode
- Validation
- Notes
* - ``enable_roce``
- driverinit
- Type: Boolean
If the device supports RoCE disablement, RoCE enablement state controls
- Boolean
- If the device supports RoCE disablement, RoCE enablement state controls
device support for RoCE capability. Otherwise, the control occurs in the
driver stack. When RoCE is disabled at the driver level, only raw
ethernet QPs are supported.
* - ``io_eq_size``
- driverinit
- The range is between 64 and 4096.
-
* - ``event_eq_size``
- driverinit
- The range is between 64 and 4096.
-
* - ``max_macs``
- driverinit
- The range is between 1 and 2^31. Only power of 2 values are supported.
-
* - ``enable_sriov``
- permanent
- Boolean
- Applies to each physical function (PF) independently, if the device
supports it. Otherwise, it applies symmetrically to all PFs.
* - ``total_vfs``
- permanent
- The range is between 1 and a device-specific max.
- Applies to each physical function (PF) independently, if the device
supports it. Otherwise, it applies symmetrically to all PFs.
Note: permanent parameters such as ``enable_sriov`` and ``total_vfs`` require FW reset to take effect
.. code-block:: bash
# setup parameters
devlink dev param set pci/0000:01:00.0 name enable_sriov value true cmode permanent
devlink dev param set pci/0000:01:00.0 name total_vfs value 8 cmode permanent
# Fw reset
devlink dev reload pci/0000:01:00.0 action fw_activate
# for PCI related config such as sriov PCI reset/rescan is required:
echo 1 >/sys/bus/pci/devices/0000:01:00.0/remove
echo 1 >/sys/bus/pci/rescan
grep ^ /sys/bus/pci/devices/0000:01:00.0/sriov_*
The ``mlx5`` driver also implements the following driver-specific
parameters.
@@ -117,6 +147,16 @@ parameters.
- driverinit
- Control the size (in packets) of the hairpin queues.
* - ``cqe_compress_type``
- string
- permanent
- Configure which mechanism/algorithm should be used by the NIC that will
affect the rate (aggressiveness) of compressed CQEs depending on PCIe bus
conditions and other internal NIC factors. This mode affects all queues
that enable compression.
* ``balanced`` : Merges fewer CQEs, resulting in a moderate compression ratio but maintaining a balance between bandwidth savings and performance
* ``aggressive`` : Merges more CQEs into a single entry, achieving a higher compression rate and maximizing performance, particularly under high traffic loads
The ``mlx5`` driver supports reloading via ``DEVLINK_CMD_RELOAD``
Info versions

2
drivers/net/ethernet/mellanox/mlx5/core/Makefile
View File

@@ -17,7 +17,7 @@ mlx5_core-y := main.o cmd.o debugfs.o fw.o eq.o uar.o pagealloc.o \
fs_counters.o fs_ft_pool.o rl.o lag/debugfs.o lag/lag.o dev.o events.o wq.o lib/gid.o \
lib/devcom.o lib/pci_vsc.o lib/dm.o lib/fs_ttc.o diag/fs_tracepoint.o \
diag/fw_tracer.o diag/crdump.o devlink.o diag/rsc_dump.o diag/reporter_vnic.o \
fw_reset.o qos.o lib/tout.o lib/aso.o wc.o fs_pool.o
fw_reset.o qos.o lib/tout.o lib/aso.o wc.o fs_pool.o lib/nv_param.o
#
# Netdev basic

8
drivers/net/ethernet/mellanox/mlx5/core/devlink.c
View File

@@ -10,6 +10,7 @@
#include "esw/qos.h"
#include "sf/dev/dev.h"
#include "sf/sf.h"
#include "lib/nv_param.h"
static int mlx5_devlink_flash_update(struct devlink *devlink,
struct devlink_flash_update_params *params,
@@ -895,8 +896,14 @@ int mlx5_devlink_params_register(struct devlink *devlink)
if (err)
goto max_uc_list_err;
err = mlx5_nv_param_register_dl_params(devlink);
if (err)
goto nv_param_err;
return 0;
nv_param_err:
mlx5_devlink_max_uc_list_params_unregister(devlink);
max_uc_list_err:
mlx5_devlink_auxdev_params_unregister(devlink);
auxdev_reg_err:
@@ -907,6 +914,7 @@ int mlx5_devlink_params_register(struct devlink *devlink)
void mlx5_devlink_params_unregister(struct devlink *devlink)
{
mlx5_nv_param_unregister_dl_params(devlink);
mlx5_devlink_max_uc_list_params_unregister(devlink);
mlx5_devlink_auxdev_params_unregister(devlink);
devl_params_unregister(devlink, mlx5_devlink_params,

1
drivers/net/ethernet/mellanox/mlx5/core/devlink.h
View File

@@ -22,6 +22,7 @@ enum mlx5_devlink_param_id {
MLX5_DEVLINK_PARAM_ID_ESW_MULTIPORT,
MLX5_DEVLINK_PARAM_ID_HAIRPIN_NUM_QUEUES,
MLX5_DEVLINK_PARAM_ID_HAIRPIN_QUEUE_SIZE,
MLX5_DEVLINK_PARAM_ID_CQE_COMPRESSION_TYPE
};
struct mlx5_trap_ctx {

576
drivers/net/ethernet/mellanox/mlx5/core/lib/nv_param.c Normal file
View File

@@ -0,0 +1,576 @@
// SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB
/* Copyright (c) 2024, NVIDIA CORPORATION & AFFILIATES. All rights reserved. */
#include "nv_param.h"
#include "mlx5_core.h"
enum {
MLX5_CLASS_0_CTRL_ID_NV_GLOBAL_PCI_CONF = 0x80,
MLX5_CLASS_0_CTRL_ID_NV_GLOBAL_PCI_CAP = 0x81,
MLX5_CLASS_0_CTRL_ID_NV_SW_OFFLOAD_CONFIG = 0x10a,
MLX5_CLASS_3_CTRL_ID_NV_PF_PCI_CONF = 0x80,
};
struct mlx5_ifc_configuration_item_type_class_global_bits {
u8 type_class[0x8];
u8 parameter_index[0x18];
};
struct mlx5_ifc_configuration_item_type_class_per_host_pf_bits {
u8 type_class[0x8];
u8 pf_index[0x6];
u8 pci_bus_index[0x8];
u8 parameter_index[0xa];
};
union mlx5_ifc_config_item_type_auto_bits {
struct mlx5_ifc_configuration_item_type_class_global_bits
configuration_item_type_class_global;
struct mlx5_ifc_configuration_item_type_class_per_host_pf_bits
configuration_item_type_class_per_host_pf;
u8 reserved_at_0[0x20];
};
struct mlx5_ifc_config_item_bits {
u8 valid[0x2];
u8 priority[0x2];
u8 header_type[0x2];
u8 ovr_en[0x1];
u8 rd_en[0x1];
u8 access_mode[0x2];
u8 reserved_at_a[0x1];
u8 writer_id[0x5];
u8 version[0x4];
u8 reserved_at_14[0x2];
u8 host_id_valid[0x1];
u8 length[0x9];
union mlx5_ifc_config_item_type_auto_bits type;
u8 reserved_at_40[0x10];
u8 crc16[0x10];
};
struct mlx5_ifc_mnvda_reg_bits {
struct mlx5_ifc_config_item_bits configuration_item_header;
u8 configuration_item_data[64][0x20];
};
struct mlx5_ifc_nv_global_pci_conf_bits {
u8 sriov_valid[0x1];
u8 reserved_at_1[0x10];
u8 per_pf_total_vf[0x1];
u8 reserved_at_12[0xe];
u8 sriov_en[0x1];
u8 reserved_at_21[0xf];
u8 total_vfs[0x10];
u8 reserved_at_40[0x20];
};
struct mlx5_ifc_nv_global_pci_cap_bits {
u8 max_vfs_per_pf_valid[0x1];
u8 reserved_at_1[0x13];
u8 per_pf_total_vf_supported[0x1];
u8 reserved_at_15[0xb];
u8 sriov_support[0x1];
u8 reserved_at_21[0xf];
u8 max_vfs_per_pf[0x10];
u8 reserved_at_40[0x60];
};
struct mlx5_ifc_nv_pf_pci_conf_bits {
u8 reserved_at_0[0x9];
u8 pf_total_vf_en[0x1];
u8 reserved_at_a[0x16];
u8 reserved_at_20[0x20];
u8 reserved_at_40[0x10];
u8 total_vf[0x10];
u8 reserved_at_60[0x20];
};
struct mlx5_ifc_nv_sw_offload_conf_bits {
u8 ip_over_vxlan_port[0x10];
u8 tunnel_ecn_copy_offload_disable[0x1];
u8 pci_atomic_mode[0x3];
u8 sr_enable[0x1];
u8 ptp_cyc2realtime[0x1];
u8 vector_calc_disable[0x1];
u8 uctx_en[0x1];
u8 prio_tag_required_en[0x1];
u8 esw_fdb_ipv4_ttl_modify_enable[0x1];
u8 mkey_by_name[0x1];
u8 ip_over_vxlan_en[0x1];
u8 one_qp_per_recovery[0x1];
u8 cqe_compression[0x3];
u8 tunnel_udp_entropy_proto_disable[0x1];
u8 reserved_at_21[0x1];
u8 ar_enable[0x1];
u8 log_max_outstanding_wqe[0x5];
u8 vf_migration[0x2];
u8 log_tx_psn_win[0x6];
u8 lro_log_timeout3[0x4];
u8 lro_log_timeout2[0x4];
u8 lro_log_timeout1[0x4];
u8 lro_log_timeout0[0x4];
};
#define MNVDA_HDR_SZ \
(MLX5_ST_SZ_BYTES(mnvda_reg) - \
MLX5_BYTE_OFF(mnvda_reg, configuration_item_data))
#define MLX5_SET_CFG_ITEM_TYPE(_cls_name, _mnvda_ptr, _field, _val) \
MLX5_SET(mnvda_reg, _mnvda_ptr, \
configuration_item_header.type.configuration_item_type_class_##_cls_name._field, \
_val)
#define MLX5_SET_CFG_HDR_LEN(_mnvda_ptr, _cls_name) \
MLX5_SET(mnvda_reg, _mnvda_ptr, configuration_item_header.length, \
MLX5_ST_SZ_BYTES(_cls_name))
#define MLX5_GET_CFG_HDR_LEN(_mnvda_ptr) \
MLX5_GET(mnvda_reg, _mnvda_ptr, configuration_item_header.length)
static int mlx5_nv_param_read(struct mlx5_core_dev *dev, void *mnvda,
size_t len)
{
u32 param_idx, type_class;
u32 header_len;
void *cls_ptr;
int err;
if (WARN_ON(len > MLX5_ST_SZ_BYTES(mnvda_reg)) || len < MNVDA_HDR_SZ)
return -EINVAL; /* A caller bug */
err = mlx5_core_access_reg(dev, mnvda, len, mnvda, len, MLX5_REG_MNVDA,
0, 0);
if (!err)
return 0;
cls_ptr = MLX5_ADDR_OF(mnvda_reg, mnvda,
configuration_item_header.type.configuration_item_type_class_global);
type_class = MLX5_GET(configuration_item_type_class_global, cls_ptr,
type_class);
param_idx = MLX5_GET(configuration_item_type_class_global, cls_ptr,
parameter_index);
header_len = MLX5_GET_CFG_HDR_LEN(mnvda);
mlx5_core_warn(dev, "Failed to read mnvda reg: type_class 0x%x, param_idx 0x%x, header_len %u, err %d\n",
type_class, param_idx, header_len, err);
return -EOPNOTSUPP;
}
static int mlx5_nv_param_write(struct mlx5_core_dev *dev, void *mnvda,
size_t len)
{
if (WARN_ON(len > MLX5_ST_SZ_BYTES(mnvda_reg)) || len < MNVDA_HDR_SZ)
return -EINVAL;
if (WARN_ON(MLX5_GET_CFG_HDR_LEN(mnvda) == 0))
return -EINVAL;
return mlx5_core_access_reg(dev, mnvda, len, mnvda, len, MLX5_REG_MNVDA,
0, 1);
}
static int
mlx5_nv_param_read_sw_offload_conf(struct mlx5_core_dev *dev, void *mnvda,
size_t len)
{
MLX5_SET_CFG_ITEM_TYPE(global, mnvda, type_class, 0);
MLX5_SET_CFG_ITEM_TYPE(global, mnvda, parameter_index,
MLX5_CLASS_0_CTRL_ID_NV_SW_OFFLOAD_CONFIG);
MLX5_SET_CFG_HDR_LEN(mnvda, nv_sw_offload_conf);
return mlx5_nv_param_read(dev, mnvda, len);
}
static const char *const
cqe_compress_str[] = { "balanced", "aggressive" };
static int
mlx5_nv_param_devlink_cqe_compress_get(struct devlink *devlink, u32 id,
struct devlink_param_gset_ctx *ctx)
{
struct mlx5_core_dev *dev = devlink_priv(devlink);
u32 mnvda[MLX5_ST_SZ_DW(mnvda_reg)] = {};
u8 value = U8_MAX;
void *data;
int err;
err = mlx5_nv_param_read_sw_offload_conf(dev, mnvda, sizeof(mnvda));
if (err)
return err;
data = MLX5_ADDR_OF(mnvda_reg, mnvda, configuration_item_data);
value = MLX5_GET(nv_sw_offload_conf, data, cqe_compression);
if (value >= ARRAY_SIZE(cqe_compress_str))
return -EOPNOTSUPP;
strscpy(ctx->val.vstr, cqe_compress_str[value], sizeof(ctx->val.vstr));
return 0;
}
static int
mlx5_nv_param_devlink_cqe_compress_validate(struct devlink *devlink, u32 id,
union devlink_param_value val,
struct netlink_ext_ack *extack)
{
int i;
for (i = 0; i < ARRAY_SIZE(cqe_compress_str); i++) {
if (!strcmp(val.vstr, cqe_compress_str[i]))
return 0;
}
NL_SET_ERR_MSG_MOD(extack,
"Invalid value, supported values are balanced/aggressive");
return -EOPNOTSUPP;
}
static int
mlx5_nv_param_devlink_cqe_compress_set(struct devlink *devlink, u32 id,
struct devlink_param_gset_ctx *ctx,
struct netlink_ext_ack *extack)
{
struct mlx5_core_dev *dev = devlink_priv(devlink);
u32 mnvda[MLX5_ST_SZ_DW(mnvda_reg)] = {};
int err = 0;
void *data;
u8 value;
if (!strcmp(ctx->val.vstr, "aggressive"))
value = 1;
else /* balanced: can't be anything else already validated above */
value = 0;
err = mlx5_nv_param_read_sw_offload_conf(dev, mnvda, sizeof(mnvda));
if (err) {
NL_SET_ERR_MSG_MOD(extack,
"Failed to read sw_offload_conf mnvda reg");
return err;
}
data = MLX5_ADDR_OF(mnvda_reg, mnvda, configuration_item_data);
MLX5_SET(nv_sw_offload_conf, data, cqe_compression, value);
return mlx5_nv_param_write(dev, mnvda, sizeof(mnvda));
}
static int mlx5_nv_param_read_global_pci_conf(struct mlx5_core_dev *dev,
void *mnvda, size_t len)
{
MLX5_SET_CFG_ITEM_TYPE(global, mnvda, type_class, 0);
MLX5_SET_CFG_ITEM_TYPE(global, mnvda, parameter_index,
MLX5_CLASS_0_CTRL_ID_NV_GLOBAL_PCI_CONF);
MLX5_SET_CFG_HDR_LEN(mnvda, nv_global_pci_conf);
return mlx5_nv_param_read(dev, mnvda, len);
}
static int mlx5_nv_param_read_global_pci_cap(struct mlx5_core_dev *dev,
void *mnvda, size_t len)
{
MLX5_SET_CFG_ITEM_TYPE(global, mnvda, type_class, 0);
MLX5_SET_CFG_ITEM_TYPE(global, mnvda, parameter_index,
MLX5_CLASS_0_CTRL_ID_NV_GLOBAL_PCI_CAP);
MLX5_SET_CFG_HDR_LEN(mnvda, nv_global_pci_cap);
return mlx5_nv_param_read(dev, mnvda, len);
}
static int mlx5_nv_param_read_per_host_pf_conf(struct mlx5_core_dev *dev,
void *mnvda, size_t len)
{
MLX5_SET_CFG_ITEM_TYPE(per_host_pf, mnvda, type_class, 3);
MLX5_SET_CFG_ITEM_TYPE(per_host_pf, mnvda, parameter_index,
MLX5_CLASS_3_CTRL_ID_NV_PF_PCI_CONF);
MLX5_SET_CFG_HDR_LEN(mnvda, nv_pf_pci_conf);
return mlx5_nv_param_read(dev, mnvda, len);
}
static int mlx5_devlink_enable_sriov_get(struct devlink *devlink, u32 id,
struct devlink_param_gset_ctx *ctx)
{
struct mlx5_core_dev *dev = devlink_priv(devlink);
u32 mnvda[MLX5_ST_SZ_DW(mnvda_reg)] = {};
bool sriov_en = false;
void *data;
int err;
err = mlx5_nv_param_read_global_pci_cap(dev, mnvda, sizeof(mnvda));
if (err)
return err;
data = MLX5_ADDR_OF(mnvda_reg, mnvda, configuration_item_data);
if (!MLX5_GET(nv_global_pci_cap, data, sriov_support)) {
ctx->val.vbool = false;
return 0;
}
memset(mnvda, 0, sizeof(mnvda));
err = mlx5_nv_param_read_global_pci_conf(dev, mnvda, sizeof(mnvda));
if (err)
return err;
data = MLX5_ADDR_OF(mnvda_reg, mnvda, configuration_item_data);
sriov_en = MLX5_GET(nv_global_pci_conf, data, sriov_en);
if (!MLX5_GET(nv_global_pci_conf, data, per_pf_total_vf)) {
ctx->val.vbool = sriov_en;
return 0;
}
/* SRIOV is per PF */
memset(mnvda, 0, sizeof(mnvda));
err = mlx5_nv_param_read_per_host_pf_conf(dev, mnvda, sizeof(mnvda));
if (err)
return err;
data = MLX5_ADDR_OF(mnvda_reg, mnvda, configuration_item_data);
ctx->val.vbool = sriov_en &&
MLX5_GET(nv_pf_pci_conf, data, pf_total_vf_en);
return 0;
}
static int mlx5_devlink_enable_sriov_set(struct devlink *devlink, u32 id,
struct devlink_param_gset_ctx *ctx,
struct netlink_ext_ack *extack)
{
struct mlx5_core_dev *dev = devlink_priv(devlink);
u32 mnvda[MLX5_ST_SZ_DW(mnvda_reg)] = {};
bool per_pf_support;
void *cap, *data;
int err;
err = mlx5_nv_param_read_global_pci_cap(dev, mnvda, sizeof(mnvda));
if (err) {
NL_SET_ERR_MSG_MOD(extack,
"Failed to read global PCI capability");
return err;
}
cap = MLX5_ADDR_OF(mnvda_reg, mnvda, configuration_item_data);
per_pf_support = MLX5_GET(nv_global_pci_cap, cap,
per_pf_total_vf_supported);
if (!MLX5_GET(nv_global_pci_cap, cap, sriov_support)) {
NL_SET_ERR_MSG_MOD(extack,
"SRIOV is not supported on this device");
return -EOPNOTSUPP;
}
if (!per_pf_support) {
/* We don't allow global SRIOV setting on per PF devlink */
NL_SET_ERR_MSG_MOD(extack,
"SRIOV is not per PF on this device");
return -EOPNOTSUPP;
}
memset(mnvda, 0, sizeof(mnvda));
err = mlx5_nv_param_read_global_pci_conf(dev, mnvda, sizeof(mnvda));
if (err) {
NL_SET_ERR_MSG_MOD(extack,
"Unable to read global PCI configuration");
return err;
}
data = MLX5_ADDR_OF(mnvda_reg, mnvda, configuration_item_data);
/* setup per PF sriov mode */
MLX5_SET(nv_global_pci_conf, data, sriov_valid, 1);
MLX5_SET(nv_global_pci_conf, data, sriov_en, 1);
MLX5_SET(nv_global_pci_conf, data, per_pf_total_vf, 1);
err = mlx5_nv_param_write(dev, mnvda, sizeof(mnvda));
if (err) {
NL_SET_ERR_MSG_MOD(extack,
"Unable to write global PCI configuration");
return err;
}
/* enable/disable sriov on this PF */
memset(mnvda, 0, sizeof(mnvda));
err = mlx5_nv_param_read_per_host_pf_conf(dev, mnvda, sizeof(mnvda));
if (err) {
NL_SET_ERR_MSG_MOD(extack,
"Unable to read per host PF configuration");
return err;
}
MLX5_SET(nv_pf_pci_conf, data, pf_total_vf_en, ctx->val.vbool);
return mlx5_nv_param_write(dev, mnvda, sizeof(mnvda));
}
static int mlx5_devlink_total_vfs_get(struct devlink *devlink, u32 id,
struct devlink_param_gset_ctx *ctx)
{
struct mlx5_core_dev *dev = devlink_priv(devlink);
u32 mnvda[MLX5_ST_SZ_DW(mnvda_reg)] = {};
void *data;
int err;
data = MLX5_ADDR_OF(mnvda_reg, mnvda, configuration_item_data);
err = mlx5_nv_param_read_global_pci_cap(dev, mnvda, sizeof(mnvda));
if (err)
return err;
if (!MLX5_GET(nv_global_pci_cap, data, sriov_support)) {
ctx->val.vu32 = 0;
return 0;
}
memset(mnvda, 0, sizeof(mnvda));
err = mlx5_nv_param_read_global_pci_conf(dev, mnvda, sizeof(mnvda));
if (err)
return err;
if (!MLX5_GET(nv_global_pci_conf, data, per_pf_total_vf)) {
ctx->val.vu32 = MLX5_GET(nv_global_pci_conf, data, total_vfs);
return 0;
}
/* SRIOV is per PF */
memset(mnvda, 0, sizeof(mnvda));
err = mlx5_nv_param_read_per_host_pf_conf(dev, mnvda, sizeof(mnvda));
if (err)
return err;
ctx->val.vu32 = MLX5_GET(nv_pf_pci_conf, data, total_vf);
return 0;
}
static int mlx5_devlink_total_vfs_set(struct devlink *devlink, u32 id,
struct devlink_param_gset_ctx *ctx,
struct netlink_ext_ack *extack)
{
struct mlx5_core_dev *dev = devlink_priv(devlink);
u32 mnvda[MLX5_ST_SZ_DW(mnvda_reg)];
bool per_pf_support;
void *data;
int err;
err = mlx5_nv_param_read_global_pci_cap(dev, mnvda, sizeof(mnvda));
if (err) {
NL_SET_ERR_MSG_MOD(extack, "Failed to read global pci cap");
return err;
}
data = MLX5_ADDR_OF(mnvda_reg, mnvda, configuration_item_data);
if (!MLX5_GET(nv_global_pci_cap, data, sriov_support)) {
NL_SET_ERR_MSG_MOD(extack, "Not configurable on this device");
return -EOPNOTSUPP;
}
per_pf_support = MLX5_GET(nv_global_pci_cap, data,
per_pf_total_vf_supported);
if (!per_pf_support) {
/* We don't allow global SRIOV setting on per PF devlink */
NL_SET_ERR_MSG_MOD(extack,
"SRIOV is not per PF on this device");
return -EOPNOTSUPP;
}
memset(mnvda, 0, sizeof(mnvda));
err = mlx5_nv_param_read_global_pci_conf(dev, mnvda, sizeof(mnvda));
if (err)
return err;
MLX5_SET(nv_global_pci_conf, data, sriov_valid, 1);
MLX5_SET(nv_global_pci_conf, data, per_pf_total_vf, per_pf_support);
if (!per_pf_support) {
MLX5_SET(nv_global_pci_conf, data, total_vfs, ctx->val.vu32);
return mlx5_nv_param_write(dev, mnvda, sizeof(mnvda));
}
/* SRIOV is per PF */
err = mlx5_nv_param_write(dev, mnvda, sizeof(mnvda));
if (err)
return err;
memset(mnvda, 0, sizeof(mnvda));
err = mlx5_nv_param_read_per_host_pf_conf(dev, mnvda, sizeof(mnvda));
if (err)
return err;
data = MLX5_ADDR_OF(mnvda_reg, mnvda, configuration_item_data);
MLX5_SET(nv_pf_pci_conf, data, total_vf, ctx->val.vu32);
return mlx5_nv_param_write(dev, mnvda, sizeof(mnvda));
}
static int mlx5_devlink_total_vfs_validate(struct devlink *devlink, u32 id,
union devlink_param_value val,
struct netlink_ext_ack *extack)
{
struct mlx5_core_dev *dev = devlink_priv(devlink);
u32 cap[MLX5_ST_SZ_DW(mnvda_reg)];
void *data;
u16 max;
int err;
data = MLX5_ADDR_OF(mnvda_reg, cap, configuration_item_data);
err = mlx5_nv_param_read_global_pci_cap(dev, cap, sizeof(cap));
if (err)
return err;
if (!MLX5_GET(nv_global_pci_cap, data, max_vfs_per_pf_valid))
return 0; /* optimistic, but set might fail later */
max = MLX5_GET(nv_global_pci_cap, data, max_vfs_per_pf);
if (val.vu16 > max) {
NL_SET_ERR_MSG_FMT_MOD(extack,
"Max allowed by device is %u", max);
return -EINVAL;
}
return 0;
}
static const struct devlink_param mlx5_nv_param_devlink_params[] = {
DEVLINK_PARAM_GENERIC(ENABLE_SRIOV, BIT(DEVLINK_PARAM_CMODE_PERMANENT),
mlx5_devlink_enable_sriov_get,
mlx5_devlink_enable_sriov_set, NULL),
DEVLINK_PARAM_GENERIC(TOTAL_VFS, BIT(DEVLINK_PARAM_CMODE_PERMANENT),
mlx5_devlink_total_vfs_get,
mlx5_devlink_total_vfs_set,
mlx5_devlink_total_vfs_validate),
DEVLINK_PARAM_DRIVER(MLX5_DEVLINK_PARAM_ID_CQE_COMPRESSION_TYPE,
"cqe_compress_type", DEVLINK_PARAM_TYPE_STRING,
BIT(DEVLINK_PARAM_CMODE_PERMANENT),
mlx5_nv_param_devlink_cqe_compress_get,
mlx5_nv_param_devlink_cqe_compress_set,
mlx5_nv_param_devlink_cqe_compress_validate),
};
int mlx5_nv_param_register_dl_params(struct devlink *devlink)
{
if (!mlx5_core_is_pf(devlink_priv(devlink)))
return 0;
return devl_params_register(devlink, mlx5_nv_param_devlink_params,
ARRAY_SIZE(mlx5_nv_param_devlink_params));
}
void mlx5_nv_param_unregister_dl_params(struct devlink *devlink)
{
if (!mlx5_core_is_pf(devlink_priv(devlink)))
return;
devl_params_unregister(devlink, mlx5_nv_param_devlink_params,
ARRAY_SIZE(mlx5_nv_param_devlink_params));
}

14
drivers/net/ethernet/mellanox/mlx5/core/lib/nv_param.h Normal file
View File

@@ -0,0 +1,14 @@
/* SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB */
/* Copyright (c) 2024, NVIDIA CORPORATION & AFFILIATES. All rights reserved. */
#ifndef __MLX5_NV_PARAM_H
#define __MLX5_NV_PARAM_H
#include <linux/mlx5/driver.h>
#include "devlink.h"
int mlx5_nv_param_register_dl_params(struct devlink *devlink);
void mlx5_nv_param_unregister_dl_params(struct devlink *devlink);
#endif

1
include/linux/mlx5/driver.h
View File

@@ -137,6 +137,7 @@ enum {
MLX5_REG_MTCAP = 0x9009,
MLX5_REG_MTMP = 0x900A,
MLX5_REG_MCIA = 0x9014,
MLX5_REG_MNVDA = 0x9024,
MLX5_REG_MFRL = 0x9028,
MLX5_REG_MLCR = 0x902b,
MLX5_REG_MRTC = 0x902d,

4
include/net/devlink.h
View File

@@ -530,6 +530,7 @@ enum devlink_param_generic_id {
DEVLINK_PARAM_GENERIC_ID_EVENT_EQ_SIZE,
DEVLINK_PARAM_GENERIC_ID_ENABLE_PHC,
DEVLINK_PARAM_GENERIC_ID_CLOCK_ID,
DEVLINK_PARAM_GENERIC_ID_TOTAL_VFS,
/* add new param generic ids above here*/
__DEVLINK_PARAM_GENERIC_ID_MAX,
@@ -594,6 +595,9 @@ enum devlink_param_generic_id {
#define DEVLINK_PARAM_GENERIC_CLOCK_ID_NAME "clock_id"
#define DEVLINK_PARAM_GENERIC_CLOCK_ID_TYPE DEVLINK_PARAM_TYPE_U64
#define DEVLINK_PARAM_GENERIC_TOTAL_VFS_NAME "total_vfs"
#define DEVLINK_PARAM_GENERIC_TOTAL_VFS_TYPE DEVLINK_PARAM_TYPE_U32
#define DEVLINK_PARAM_GENERIC(_id, _cmodes, _get, _set, _validate) \
{ \
.id = DEVLINK_PARAM_GENERIC_ID_##_id, \

5
net/devlink/param.c
View File

@@ -102,6 +102,11 @@ static const struct devlink_param devlink_param_generic[] = {
.name = DEVLINK_PARAM_GENERIC_CLOCK_ID_NAME,
.type = DEVLINK_PARAM_GENERIC_CLOCK_ID_TYPE,
},
{
.id = DEVLINK_PARAM_GENERIC_ID_TOTAL_VFS,
.name = DEVLINK_PARAM_GENERIC_TOTAL_VFS_NAME,
.type = DEVLINK_PARAM_GENERIC_TOTAL_VFS_TYPE,
},
};
static int devlink_param_generic_verify(const struct devlink_param *param)