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dt-bindings: net: fsl,gianfar-mdio: Update information about TBI

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When this binding was originally written, all known TSEC Ethernet
controllers had a Ten-Bit Interface (TBI). However, some datasheets such
as for the MPC8315E suggest that this is not universally true:

  The eTSECs do not support TBI, GMII, and FIFO operating modes, so all
  references to these interfaces and features should be ignored for this
  device.

Acked-by: Rob Herring (Arm) <robh@kernel.org>
Signed-off-by: J. Neuschäfer <j.ne@posteo.net>
Link: https://patch.msgid.link/20250228-gianfar-yaml-v2-2-6beeefbd4818@posteo.net
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
This commit is contained in:
J. Neuschäfer
2025-02-28 18:32:51 +01:00
committed by Jakub Kicinski
parent e4c4522390
commit 0386e29e60
1 changed files with 6 additions and 7 deletions
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13
Documentation/devicetree/bindings/net/fsl,gianfar-mdio.yaml
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@@ -11,13 +11,12 @@ description:
connected. For each device that exists on this bus, a child node should be
created.
As of this writing, every TSEC is associated with an internal Ten-Bit
Interface (TBI) PHY. This PHY is accessed through the local MDIO bus. These
buses are defined similarly to the mdio buses, except they are compatible
with "fsl,gianfar-tbi". The TBI PHYs underneath them are similar to normal
PHYs, but the reg property is considered instructive, rather than
descriptive. The reg property should be chosen so it doesn't interfere with
other PHYs on the bus.
Some TSECs are associated with an internal Ten-Bit Interface (TBI) PHY. This
PHY is accessed through the local MDIO bus. These buses are defined similarly
to the mdio buses, except they are compatible with "fsl,gianfar-tbi". The TBI
PHYs underneath them are similar to normal PHYs, but the reg property is
considered instructive, rather than descriptive. The reg property should be
chosen so it doesn't interfere with other PHYs on the bus.
maintainers:
- J. Neuschäfer <j.ne@posteo.net>