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staging: wilc1000: refactor SPI read/write commands handling API's

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Refactor SPI commands handling by making use of 'struct' for data
exchange and extraction of information flow between host and firmware.
The SPI read/write commands are now handled in separate function instead
of using a single function to process all types of command.
The use of 'struct' helped to make the code self explanatory. These
points were discussed and suggested during code review [1].

1. https://www.spinics.net/lists/linux-wireless/msg191489.html

Signed-off-by: Ajay Singh <ajay.kathat@microchip.com>
Link: https://lore.kernel.org/r/20200203160848.4052-1-ajay.kathat@microchip.com
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This commit is contained in:
Ajay Singh
2020-02-03 10:39:43 +00:00
committed by Greg Kroah-Hartman
parent 8e2e79ff61
commit 034280e33e
1 changed files with 405 additions and 411 deletions
Download Patch File Download Diff File Expand all files Collapse all files

816
drivers/staging/wilc1000/spi.c
View File

@@ -70,6 +70,11 @@ static u8 crc7(u8 crc, const u8 *buffer, u32 len)
return crc;
}
static u8 wilc_get_crc7(u8 *buffer, u32 len)
{
return crc7(0x7f, (const u8 *)buffer, len) << 1;
}
/********************************************
*
* Spi protocol Function
@@ -97,6 +102,52 @@ static u8 crc7(u8 crc, const u8 *buffer, u32 len)
#define USE_SPI_DMA 0
#define WILC_SPI_COMMAND_STAT_SUCCESS 0
#define WILC_GET_RESP_HDR_START(h) (((h) >> 4) & 0xf)
struct wilc_spi_cmd {
u8 cmd_type;
union {
struct {
u8 addr[3];
u8 crc[0];
} __packed simple_cmd;
struct {
u8 addr[3];
u8 size[2];
u8 crc[0];
} __packed dma_cmd;
struct {
u8 addr[3];
u8 size[3];
u8 crc[0];
} __packed dma_cmd_ext;
struct {
u8 addr[2];
__be32 data;
u8 crc[0];
} __packed internal_w_cmd;
struct {
u8 addr[3];
__be32 data;
u8 crc[0];
} __packed w_cmd;
} u;
} __packed;
struct wilc_spi_read_rsp_data {
u8 rsp_cmd_type;
u8 status;
u8 resp_header;
u8 resp_data[4];
u8 crc[0];
} __packed;
struct wilc_spi_rsp_data {
u8 rsp_cmd_type;
u8 status;
} __packed;
static int wilc_bus_probe(struct spi_device *spi)
{
int ret;
@@ -284,335 +335,6 @@ static int wilc_spi_tx_rx(struct wilc *wilc, u8 *wb, u8 *rb, u32 rlen)
return ret;
}
static int spi_cmd_complete(struct wilc *wilc, u8 cmd, u32 adr, u8 *b, u32 sz,
u8 clockless)
{
struct spi_device *spi = to_spi_device(wilc->dev);
struct wilc_spi *spi_priv = wilc->bus_data;
u8 wb[32], rb[32];
u8 wix, rix;
u32 len2;
u8 rsp;
int len = 0;
int result = 0;
int retry;
u8 crc[2];
wb[0] = cmd;
switch (cmd) {
case CMD_SINGLE_READ: /* single word (4 bytes) read */
wb[1] = (u8)(adr >> 16);
wb[2] = (u8)(adr >> 8);
wb[3] = (u8)adr;
len = 5;
break;
case CMD_INTERNAL_READ: /* internal register read */
wb[1] = (u8)(adr >> 8);
if (clockless == 1)
wb[1] |= BIT(7);
wb[2] = (u8)adr;
wb[3] = 0x00;
len = 5;
break;
case CMD_TERMINATE:
wb[1] = 0x00;
wb[2] = 0x00;
wb[3] = 0x00;
len = 5;
break;
case CMD_REPEAT:
wb[1] = 0x00;
wb[2] = 0x00;
wb[3] = 0x00;
len = 5;
break;
case CMD_RESET:
wb[1] = 0xff;
wb[2] = 0xff;
wb[3] = 0xff;
len = 5;
break;
case CMD_DMA_WRITE: /* dma write */
case CMD_DMA_READ: /* dma read */
wb[1] = (u8)(adr >> 16);
wb[2] = (u8)(adr >> 8);
wb[3] = (u8)adr;
wb[4] = (u8)(sz >> 8);
wb[5] = (u8)(sz);
len = 7;
break;
case CMD_DMA_EXT_WRITE: /* dma extended write */
case CMD_DMA_EXT_READ: /* dma extended read */
wb[1] = (u8)(adr >> 16);
wb[2] = (u8)(adr >> 8);
wb[3] = (u8)adr;
wb[4] = (u8)(sz >> 16);
wb[5] = (u8)(sz >> 8);
wb[6] = (u8)(sz);
len = 8;
break;
case CMD_INTERNAL_WRITE: /* internal register write */
wb[1] = (u8)(adr >> 8);
if (clockless == 1)
wb[1] |= BIT(7);
wb[2] = (u8)(adr);
wb[3] = b[3];
wb[4] = b[2];
wb[5] = b[1];
wb[6] = b[0];
len = 8;
break;
case CMD_SINGLE_WRITE: /* single word write */
wb[1] = (u8)(adr >> 16);
wb[2] = (u8)(adr >> 8);
wb[3] = (u8)(adr);
wb[4] = b[3];
wb[5] = b[2];
wb[6] = b[1];
wb[7] = b[0];
len = 9;
break;
default:
result = -EINVAL;
break;
}
if (result)
return result;
if (!spi_priv->crc_off)
wb[len - 1] = (crc7(0x7f, (const u8 *)&wb[0], len - 1)) << 1;
else
len -= 1;
#define NUM_SKIP_BYTES (1)
#define NUM_RSP_BYTES (2)
#define NUM_DATA_HDR_BYTES (1)
#define NUM_DATA_BYTES (4)
#define NUM_CRC_BYTES (2)
#define NUM_DUMMY_BYTES (3)
if (cmd == CMD_RESET ||
cmd == CMD_TERMINATE ||
cmd == CMD_REPEAT) {
len2 = len + (NUM_SKIP_BYTES + NUM_RSP_BYTES + NUM_DUMMY_BYTES);
} else if (cmd == CMD_INTERNAL_READ || cmd == CMD_SINGLE_READ) {
int tmp = NUM_RSP_BYTES + NUM_DATA_HDR_BYTES + NUM_DATA_BYTES
+ NUM_DUMMY_BYTES;
if (!spi_priv->crc_off)
len2 = len + tmp + NUM_CRC_BYTES;
else
len2 = len + tmp;
} else {
len2 = len + (NUM_RSP_BYTES + NUM_DUMMY_BYTES);
}
#undef NUM_DUMMY_BYTES
if (len2 > ARRAY_SIZE(wb)) {
dev_err(&spi->dev, "spi buffer size too small (%d) (%zu)\n",
len2, ARRAY_SIZE(wb));
return -EINVAL;
}
/* zero spi write buffers. */
for (wix = len; wix < len2; wix++)
wb[wix] = 0;
rix = len;
if (wilc_spi_tx_rx(wilc, wb, rb, len2)) {
dev_err(&spi->dev, "Failed cmd write, bus error...\n");
return -EINVAL;
}
/*
* Command/Control response
*/
if (cmd == CMD_RESET || cmd == CMD_TERMINATE || cmd == CMD_REPEAT)
rix++; /* skip 1 byte */
rsp = rb[rix++];
if (rsp != cmd) {
dev_err(&spi->dev,
"Failed cmd response, cmd (%02x), resp (%02x)\n",
cmd, rsp);
return -EINVAL;
}
/*
* State response
*/
rsp = rb[rix++];
if (rsp != 0x00) {
dev_err(&spi->dev, "Failed cmd state response state (%02x)\n",
rsp);
return -EINVAL;
}
if (cmd == CMD_INTERNAL_READ || cmd == CMD_SINGLE_READ ||
cmd == CMD_DMA_READ || cmd == CMD_DMA_EXT_READ) {
/*
* Data Respnose header
*/
retry = 100;
do {
/*
* ensure there is room in buffer later
* to read data and crc
*/
if (rix < len2) {
rsp = rb[rix++];
} else {
retry = 0;
break;
}
if (((rsp >> 4) & 0xf) == 0xf)
break;
} while (retry--);
if (retry <= 0) {
dev_err(&spi->dev,
"Error, data read response (%02x)\n", rsp);
return -EAGAIN;
}
}
if (cmd == CMD_INTERNAL_READ || cmd == CMD_SINGLE_READ) {
/*
* Read bytes
*/
if ((rix + 3) < len2) {
b[0] = rb[rix++];
b[1] = rb[rix++];
b[2] = rb[rix++];
b[3] = rb[rix++];
} else {
dev_err(&spi->dev,
"buffer overrun when reading data.\n");
return -EINVAL;
}
if (!spi_priv->crc_off) {
/*
* Read Crc
*/
if ((rix + 1) < len2) {
crc[0] = rb[rix++];
crc[1] = rb[rix++];
} else {
dev_err(&spi->dev,
"buffer overrun when reading crc.\n");
return -EINVAL;
}
}
} else if ((cmd == CMD_DMA_READ) || (cmd == CMD_DMA_EXT_READ)) {
int ix;
/* some data may be read in response to dummy bytes. */
for (ix = 0; (rix < len2) && (ix < sz); )
b[ix++] = rb[rix++];
sz -= ix;
if (sz > 0) {
int nbytes;
if (sz <= (DATA_PKT_SZ - ix))
nbytes = sz;
else
nbytes = DATA_PKT_SZ - ix;
/*
* Read bytes
*/
if (wilc_spi_rx(wilc, &b[ix], nbytes)) {
dev_err(&spi->dev,
"Failed block read, bus err\n");
return -EINVAL;
}
/*
* Read Crc
*/
if (!spi_priv->crc_off && wilc_spi_rx(wilc, crc, 2)) {
dev_err(&spi->dev,
"Failed block crc read, bus err\n");
return -EINVAL;
}
ix += nbytes;
sz -= nbytes;
}
/*
* if any data in left unread,
* then read the rest using normal DMA code.
*/
while (sz > 0) {
int nbytes;
if (sz <= DATA_PKT_SZ)
nbytes = sz;
else
nbytes = DATA_PKT_SZ;
/*
* read data response only on the next DMA cycles not
* the first DMA since data response header is already
* handled above for the first DMA.
*/
/*
* Data Respnose header
*/
retry = 10;
do {
if (wilc_spi_rx(wilc, &rsp, 1)) {
dev_err(&spi->dev,
"Failed resp read, bus err\n");
result = -EINVAL;
break;
}
if (((rsp >> 4) & 0xf) == 0xf)
break;
} while (retry--);
if (result)
break;
/*
* Read bytes
*/
if (wilc_spi_rx(wilc, &b[ix], nbytes)) {
dev_err(&spi->dev,
"Failed block read, bus err\n");
result = -EINVAL;
break;
}
/*
* Read Crc
*/
if (!spi_priv->crc_off && wilc_spi_rx(wilc, crc, 2)) {
dev_err(&spi->dev,
"Failed block crc read, bus err\n");
result = -EINVAL;
break;
}
ix += nbytes;
sz -= nbytes;
}
}
return result;
}
static int spi_data_write(struct wilc *wilc, u8 *b, u32 sz)
{
struct spi_device *spi = to_spi_device(wilc->dev);
@@ -686,91 +408,273 @@ static int spi_data_write(struct wilc *wilc, u8 *b, u32 sz)
* Spi Internal Read/Write Function
*
********************************************/
static int spi_internal_write(struct wilc *wilc, u32 adr, u32 dat)
static int wilc_spi_single_read(struct wilc *wilc, u8 cmd, u32 adr, void *b,
u8 clockless)
{
struct spi_device *spi = to_spi_device(wilc->dev);
int result;
struct wilc_spi *spi_priv = wilc->bus_data;
u8 wb[32], rb[32];
int cmd_len, resp_len;
u8 crc[2];
struct wilc_spi_cmd *c;
struct wilc_spi_read_rsp_data *r;
cpu_to_le32s(&dat);
result = spi_cmd_complete(wilc, CMD_INTERNAL_WRITE, adr, (u8 *)&dat, 4,
0);
if (result)
dev_err(&spi->dev, "Failed internal write cmd...\n");
return result;
}
static int spi_internal_read(struct wilc *wilc, u32 adr, u32 *data)
{
struct spi_device *spi = to_spi_device(wilc->dev);
int result;
result = spi_cmd_complete(wilc, CMD_INTERNAL_READ, adr, (u8 *)data, 4,
0);
if (result) {
dev_err(&spi->dev, "Failed internal read cmd...\n");
return result;
}
le32_to_cpus(data);
return result;
}
/********************************************
*
* Spi interfaces
*
********************************************/
static int wilc_spi_write_reg(struct wilc *wilc, u32 addr, u32 data)
{
struct spi_device *spi = to_spi_device(wilc->dev);
int result;
u8 cmd = CMD_SINGLE_WRITE;
u8 clockless = 0;
cpu_to_le32s(&data);
if (addr < 0x30) {
/* Clockless register */
cmd = CMD_INTERNAL_WRITE;
clockless = 1;
}
result = spi_cmd_complete(wilc, cmd, addr, (u8 *)&data, 4, clockless);
if (result)
dev_err(&spi->dev, "Failed cmd, write reg (%08x)...\n", addr);
return result;
}
static int wilc_spi_write(struct wilc *wilc, u32 addr, u8 *buf, u32 size)
{
struct spi_device *spi = to_spi_device(wilc->dev);
int result;
/*
* has to be greated than 4
*/
if (size <= 4)
memset(wb, 0x0, sizeof(wb));
memset(rb, 0x0, sizeof(rb));
c = (struct wilc_spi_cmd *)wb;
c->cmd_type = cmd;
if (cmd == CMD_SINGLE_READ) {
c->u.simple_cmd.addr[0] = adr >> 16;
c->u.simple_cmd.addr[1] = adr >> 8;
c->u.simple_cmd.addr[2] = adr;
} else if (cmd == CMD_INTERNAL_READ) {
c->u.simple_cmd.addr[0] = adr >> 8;
if (clockless == 1)
c->u.simple_cmd.addr[0] |= BIT(7);
c->u.simple_cmd.addr[1] = adr;
c->u.simple_cmd.addr[2] = 0x0;
} else {
dev_err(&spi->dev, "cmd [%x] not supported\n", cmd);
return -EINVAL;
result = spi_cmd_complete(wilc, CMD_DMA_EXT_WRITE, addr, NULL, size, 0);
if (result) {
dev_err(&spi->dev,
"Failed cmd, write block (%08x)...\n", addr);
return result;
}
/*
* Data
*/
result = spi_data_write(wilc, buf, size);
if (result)
dev_err(&spi->dev, "Failed block data write...\n");
cmd_len = offsetof(struct wilc_spi_cmd, u.simple_cmd.crc);
resp_len = sizeof(*r);
if (!spi_priv->crc_off) {
c->u.simple_cmd.crc[0] = wilc_get_crc7(wb, cmd_len);
cmd_len += 1;
resp_len += 2;
}
return result;
if (cmd_len + resp_len > ARRAY_SIZE(wb)) {
dev_err(&spi->dev,
"spi buffer size too small (%d) (%d) (%zu)\n",
cmd_len, resp_len, ARRAY_SIZE(wb));
return -EINVAL;
}
if (wilc_spi_tx_rx(wilc, wb, rb, cmd_len + resp_len)) {
dev_err(&spi->dev, "Failed cmd write, bus error...\n");
return -EINVAL;
}
r = (struct wilc_spi_read_rsp_data *)&rb[cmd_len];
if (r->rsp_cmd_type != cmd) {
dev_err(&spi->dev,
"Failed cmd response, cmd (%02x), resp (%02x)\n",
cmd, r->rsp_cmd_type);
return -EINVAL;
}
if (r->status != WILC_SPI_COMMAND_STAT_SUCCESS) {
dev_err(&spi->dev, "Failed cmd state response state (%02x)\n",
r->status);
return -EINVAL;
}
if (WILC_GET_RESP_HDR_START(r->resp_header) != 0xf) {
dev_err(&spi->dev, "Error, data read response (%02x)\n",
r->resp_header);
return -EINVAL;
}
if (b)
memcpy(b, r->resp_data, 4);
if (!spi_priv->crc_off)
memcpy(crc, r->crc, 2);
return 0;
}
static int wilc_spi_write_cmd(struct wilc *wilc, u8 cmd, u32 adr, u32 data,
u8 clockless)
{
struct spi_device *spi = to_spi_device(wilc->dev);
struct wilc_spi *spi_priv = wilc->bus_data;
u8 wb[32], rb[32];
int cmd_len, resp_len;
struct wilc_spi_cmd *c;
struct wilc_spi_rsp_data *r;
memset(wb, 0x0, sizeof(wb));
memset(rb, 0x0, sizeof(rb));
c = (struct wilc_spi_cmd *)wb;
c->cmd_type = cmd;
if (cmd == CMD_INTERNAL_WRITE) {
c->u.internal_w_cmd.addr[0] = adr >> 8;
if (clockless == 1)
c->u.internal_w_cmd.addr[0] |= BIT(7);
c->u.internal_w_cmd.addr[1] = adr;
c->u.internal_w_cmd.data = cpu_to_be32(data);
cmd_len = offsetof(struct wilc_spi_cmd, u.internal_w_cmd.crc);
if (!spi_priv->crc_off)
c->u.internal_w_cmd.crc[0] = wilc_get_crc7(wb, cmd_len);
} else if (cmd == CMD_SINGLE_WRITE) {
c->u.w_cmd.addr[0] = adr >> 16;
c->u.w_cmd.addr[1] = adr >> 8;
c->u.w_cmd.addr[2] = adr;
c->u.w_cmd.data = cpu_to_be32(data);
cmd_len = offsetof(struct wilc_spi_cmd, u.w_cmd.crc);
if (!spi_priv->crc_off)
c->u.w_cmd.crc[0] = wilc_get_crc7(wb, cmd_len);
} else {
dev_err(&spi->dev, "write cmd [%x] not supported\n", cmd);
return -EINVAL;
}
if (!spi_priv->crc_off)
cmd_len += 1;
resp_len = sizeof(*r);
if (cmd_len + resp_len > ARRAY_SIZE(wb)) {
dev_err(&spi->dev,
"spi buffer size too small (%d) (%d) (%zu)\n",
cmd_len, resp_len, ARRAY_SIZE(wb));
return -EINVAL;
}
if (wilc_spi_tx_rx(wilc, wb, rb, cmd_len + resp_len)) {
dev_err(&spi->dev, "Failed cmd write, bus error...\n");
return -EINVAL;
}
r = (struct wilc_spi_rsp_data *)&rb[cmd_len];
if (r->rsp_cmd_type != cmd) {
dev_err(&spi->dev,
"Failed cmd response, cmd (%02x), resp (%02x)\n",
cmd, r->rsp_cmd_type);
return -EINVAL;
}
if (r->status != WILC_SPI_COMMAND_STAT_SUCCESS) {
dev_err(&spi->dev, "Failed cmd state response state (%02x)\n",
r->status);
return -EINVAL;
}
return 0;
}
static int wilc_spi_dma_rw(struct wilc *wilc, u8 cmd, u32 adr, u8 *b, u32 sz)
{
struct spi_device *spi = to_spi_device(wilc->dev);
struct wilc_spi *spi_priv = wilc->bus_data;
u8 wb[32], rb[32];
int cmd_len, resp_len;
int retry, ix = 0;
u8 crc[2];
struct wilc_spi_cmd *c;
struct wilc_spi_rsp_data *r;
memset(wb, 0x0, sizeof(wb));
memset(rb, 0x0, sizeof(rb));
c = (struct wilc_spi_cmd *)wb;
c->cmd_type = cmd;
if (cmd == CMD_DMA_WRITE || cmd == CMD_DMA_READ) {
c->u.dma_cmd.addr[0] = adr >> 16;
c->u.dma_cmd.addr[1] = adr >> 8;
c->u.dma_cmd.addr[2] = adr;
c->u.dma_cmd.size[0] = sz >> 8;
c->u.dma_cmd.size[1] = sz;
cmd_len = offsetof(struct wilc_spi_cmd, u.dma_cmd.crc);
if (!spi_priv->crc_off)
c->u.dma_cmd.crc[0] = wilc_get_crc7(wb, cmd_len);
} else if (cmd == CMD_DMA_EXT_WRITE || cmd == CMD_DMA_EXT_READ) {
c->u.dma_cmd_ext.addr[0] = adr >> 16;
c->u.dma_cmd_ext.addr[1] = adr >> 8;
c->u.dma_cmd_ext.addr[2] = adr;
c->u.dma_cmd_ext.size[0] = sz >> 16;
c->u.dma_cmd_ext.size[1] = sz >> 8;
c->u.dma_cmd_ext.size[2] = sz;
cmd_len = offsetof(struct wilc_spi_cmd, u.dma_cmd_ext.crc);
if (!spi_priv->crc_off)
c->u.dma_cmd_ext.crc[0] = wilc_get_crc7(wb, cmd_len);
} else {
dev_err(&spi->dev, "dma read write cmd [%x] not supported\n",
cmd);
return -EINVAL;
}
if (!spi_priv->crc_off)
cmd_len += 1;
resp_len = sizeof(*r);
if (cmd_len + resp_len > ARRAY_SIZE(wb)) {
dev_err(&spi->dev, "spi buffer size too small (%d)(%d) (%zu)\n",
cmd_len, resp_len, ARRAY_SIZE(wb));
return -EINVAL;
}
if (wilc_spi_tx_rx(wilc, wb, rb, cmd_len + resp_len)) {
dev_err(&spi->dev, "Failed cmd write, bus error...\n");
return -EINVAL;
}
r = (struct wilc_spi_rsp_data *)&rb[cmd_len];
if (r->rsp_cmd_type != cmd) {
dev_err(&spi->dev,
"Failed cmd response, cmd (%02x), resp (%02x)\n",
cmd, r->rsp_cmd_type);
return -EINVAL;
}
if (r->status != WILC_SPI_COMMAND_STAT_SUCCESS) {
dev_err(&spi->dev, "Failed cmd state response state (%02x)\n",
r->status);
return -EINVAL;
}
if (cmd == CMD_DMA_WRITE || cmd == CMD_DMA_EXT_WRITE)
return 0;
while (sz > 0) {
int nbytes;
u8 rsp;
if (sz <= DATA_PKT_SZ)
nbytes = sz;
else
nbytes = DATA_PKT_SZ;
/*
* Data Response header
*/
retry = 100;
do {
if (wilc_spi_rx(wilc, &rsp, 1)) {
dev_err(&spi->dev,
"Failed resp read, bus err\n");
return -EINVAL;
}
if (WILC_GET_RESP_HDR_START(rsp) == 0xf)
break;
} while (retry--);
/*
* Read bytes
*/
if (wilc_spi_rx(wilc, &b[ix], nbytes)) {
dev_err(&spi->dev,
"Failed block read, bus err\n");
return -EINVAL;
}
/*
* Read Crc
*/
if (!spi_priv->crc_off && wilc_spi_rx(wilc, crc, 2)) {
dev_err(&spi->dev,
"Failed block crc read, bus err\n");
return -EINVAL;
}
ix += nbytes;
sz -= nbytes;
}
return 0;
}
static int wilc_spi_read_reg(struct wilc *wilc, u32 addr, u32 *data)
@@ -786,7 +690,7 @@ static int wilc_spi_read_reg(struct wilc *wilc, u32 addr, u32 *data)
clockless = 1;
}
result = spi_cmd_complete(wilc, cmd, addr, (u8 *)data, 4, clockless);
result = wilc_spi_single_read(wilc, cmd, addr, data, clockless);
if (result) {
dev_err(&spi->dev, "Failed cmd, read reg (%08x)...\n", addr);
return result;
@@ -805,11 +709,101 @@ static int wilc_spi_read(struct wilc *wilc, u32 addr, u8 *buf, u32 size)
if (size <= 4)
return -EINVAL;
result = spi_cmd_complete(wilc, CMD_DMA_EXT_READ, addr, buf, size, 0);
if (result)
result = wilc_spi_dma_rw(wilc, CMD_DMA_EXT_READ, addr, buf, size);
if (result) {
dev_err(&spi->dev, "Failed cmd, read block (%08x)...\n", addr);
return result;
}
return result;
return 0;
}
static int spi_internal_write(struct wilc *wilc, u32 adr, u32 dat)
{
struct spi_device *spi = to_spi_device(wilc->dev);
int result;
result = wilc_spi_write_cmd(wilc, CMD_INTERNAL_WRITE, adr, dat, 0);
if (result) {
dev_err(&spi->dev, "Failed internal write cmd...\n");
return result;
}
return 0;
}
static int spi_internal_read(struct wilc *wilc, u32 adr, u32 *data)
{
struct spi_device *spi = to_spi_device(wilc->dev);
int result;
result = wilc_spi_single_read(wilc, CMD_INTERNAL_READ, adr, data, 0);
if (result) {
dev_err(&spi->dev, "Failed internal read cmd...\n");
return result;
}
le32_to_cpus(data);
return 0;
}
/********************************************
*
* Spi interfaces
*
********************************************/
static int wilc_spi_write_reg(struct wilc *wilc, u32 addr, u32 data)
{
struct spi_device *spi = to_spi_device(wilc->dev);
int result;
u8 cmd = CMD_SINGLE_WRITE;
u8 clockless = 0;
if (addr < 0x30) {
/* Clockless register */
cmd = CMD_INTERNAL_WRITE;
clockless = 1;
}
result = wilc_spi_write_cmd(wilc, cmd, addr, data, clockless);
if (result) {
dev_err(&spi->dev, "Failed cmd, write reg (%08x)...\n", addr);
return result;
}
return 0;
}
static int wilc_spi_write(struct wilc *wilc, u32 addr, u8 *buf, u32 size)
{
struct spi_device *spi = to_spi_device(wilc->dev);
int result;
/*
* has to be greated than 4
*/
if (size <= 4)
return -EINVAL;
result = wilc_spi_dma_rw(wilc, CMD_DMA_EXT_WRITE, addr, NULL, size);
if (result) {
dev_err(&spi->dev,
"Failed cmd, write block (%08x)...\n", addr);
return result;
}
/*
* Data
*/
result = spi_data_write(wilc, buf, size);
if (result) {
dev_err(&spi->dev, "Failed block data write...\n");
return result;
}
return 0;
}
/********************************************