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Merge branch '1GbE' of git://git.kernel.org/pub/scm/linux/kernel/git/tnguy/next-queue

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Tony Nguyen says:

====================
Intel Wired LAN Driver Updates 2022-09-08 (e1000e, igc)

This series contains updates to e1000e and igc drivers.

Li Zhong adds checking and handling for failed PHY register reads for
e1000e.

Sasha removes an unused define for igc.
====================

Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
David S. Miller
2022-09-16 12:15:15 +01:00
parent ec3f06b542 2c5e5abf1c
commit 030eed86cb
2 changed files with 17 additions and 4 deletions
Download Patch File Download Diff File Expand all files Collapse all files

20
drivers/net/ethernet/intel/e1000e/phy.c
View File

@@ -2697,9 +2697,14 @@ static s32 e1000_access_phy_wakeup_reg_bm(struct e1000_hw *hw, u32 offset,
void e1000_power_up_phy_copper(struct e1000_hw *hw)
{
u16 mii_reg = 0;
int ret;
/* The PHY will retain its settings across a power down/up cycle */
e1e_rphy(hw, MII_BMCR, &mii_reg);
ret = e1e_rphy(hw, MII_BMCR, &mii_reg);
if (ret) {
e_dbg("Error reading PHY register\n");
return;
}
mii_reg &= ~BMCR_PDOWN;
e1e_wphy(hw, MII_BMCR, mii_reg);
}
@@ -2715,9 +2720,14 @@ void e1000_power_up_phy_copper(struct e1000_hw *hw)
void e1000_power_down_phy_copper(struct e1000_hw *hw)
{
u16 mii_reg = 0;
int ret;
/* The PHY will retain its settings across a power down/up cycle */
e1e_rphy(hw, MII_BMCR, &mii_reg);
ret = e1e_rphy(hw, MII_BMCR, &mii_reg);
if (ret) {
e_dbg("Error reading PHY register\n");
return;
}
mii_reg |= BMCR_PDOWN;
e1e_wphy(hw, MII_BMCR, mii_reg);
usleep_range(1000, 2000);
@@ -3037,7 +3047,11 @@ s32 e1000_link_stall_workaround_hv(struct e1000_hw *hw)
return 0;
/* Do not apply workaround if in PHY loopback bit 14 set */
e1e_rphy(hw, MII_BMCR, &data);
ret_val = e1e_rphy(hw, MII_BMCR, &data);
if (ret_val) {
e_dbg("Error reading PHY register\n");
return ret_val;
}
if (data & BMCR_LOOPBACK)
return 0;

1
drivers/net/ethernet/intel/igc/igc_defines.h
View File

@@ -610,7 +610,6 @@
#define IGC_MDIC_OP_WRITE 0x04000000
#define IGC_MDIC_OP_READ 0x08000000
#define IGC_MDIC_READY 0x10000000
#define IGC_MDIC_INT_EN 0x20000000
#define IGC_MDIC_ERROR 0x40000000
#define IGC_N0_QUEUE -1