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drm/amd/display: revert "Update scaler recout data for visual confirm"

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This reverts commit 1068e987ad.

A regression is found on this change, so revert it for the time being
and resubmit when issue is fixed.

Reviewed-by: Martin Leung <Martin.Leung@amd.com>
Acked-by: Alan Liu <HaoPing.Liu@amd.com>
Signed-off-by: Leo Ma <hanghong.ma@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Leo Ma
2023-04-21 09:58:25 -04:00
committed by Alex Deucher
parent f835a571ec
commit 029c85adcc
2 changed files with 17 additions and 18 deletions
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17
drivers/gpu/drm/amd/display/dc/core/dc_resource.c
View File

@@ -69,9 +69,6 @@
#include "../dcn32/dcn32_resource.h"
#include "../dcn321/dcn321_resource.h"
#define VISUAL_CONFIRM_RECT_HEIGHT_DEFAULT 3
#define VISUAL_CONFIRM_RECT_HEIGHT_MIN 1
#define VISUAL_CONFIRM_RECT_HEIGHT_MAX 10
#define DC_LOGGER_INIT(logger)
@@ -811,8 +808,6 @@ static void calculate_recout(struct pipe_ctx *pipe_ctx)
struct rect surf_clip = plane_state->clip_rect;
bool split_tb = stream->view_format == VIEW_3D_FORMAT_TOP_AND_BOTTOM;
int split_count, split_idx;
struct dpp *dpp = pipe_ctx->plane_res.dpp;
unsigned short visual_confirm_rect_height = VISUAL_CONFIRM_RECT_HEIGHT_DEFAULT;
calculate_split_count_and_index(pipe_ctx, &split_count, &split_idx);
if (stream->view_format == VIEW_3D_FORMAT_SIDE_BY_SIDE)
@@ -881,18 +876,6 @@ static void calculate_recout(struct pipe_ctx *pipe_ctx)
data->recout.width = data->h_active - data->recout.x;
}
}
/* Check bounds to ensure the VC bar height was set to a sane value */
if (dpp != NULL) {
if ((dpp->ctx->dc->debug.visual_confirm_rect_height >= VISUAL_CONFIRM_RECT_HEIGHT_MIN) &&
(dpp->ctx->dc->debug.visual_confirm_rect_height <= VISUAL_CONFIRM_RECT_HEIGHT_MAX)) {
visual_confirm_rect_height = dpp->ctx->dc->debug.visual_confirm_rect_height;
}
if (dpp->ctx->dc->debug.visual_confirm != VISUAL_CONFIRM_DISABLE)
data->recout.height = data->recout.height -
2 * (dpp->inst + visual_confirm_rect_height);
}
}
static void calculate_scaling_ratios(struct pipe_ctx *pipe_ctx)

18
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c
View File

@@ -39,6 +39,9 @@
#define BLACK_OFFSET_RGB_Y 0x0
#define BLACK_OFFSET_CBCR 0x8000
#define VISUAL_CONFIRM_RECT_HEIGHT_DEFAULT 3
#define VISUAL_CONFIRM_RECT_HEIGHT_MIN 1
#define VISUAL_CONFIRM_RECT_HEIGHT_MAX 10
#define REG(reg)\
dpp->tf_regs->reg
@@ -588,6 +591,18 @@ static void dpp1_dscl_set_manual_ratio_init(
static void dpp1_dscl_set_recout(struct dcn10_dpp *dpp,
const struct rect *recout)
{
int visual_confirm_on = 0;
unsigned short visual_confirm_rect_height = VISUAL_CONFIRM_RECT_HEIGHT_DEFAULT;
if (dpp->base.ctx->dc->debug.visual_confirm != VISUAL_CONFIRM_DISABLE)
visual_confirm_on = 1;
/* Check bounds to ensure the VC bar height was set to a sane value */
if ((dpp->base.ctx->dc->debug.visual_confirm_rect_height >= VISUAL_CONFIRM_RECT_HEIGHT_MIN) &&
(dpp->base.ctx->dc->debug.visual_confirm_rect_height <= VISUAL_CONFIRM_RECT_HEIGHT_MAX)) {
visual_confirm_rect_height = dpp->base.ctx->dc->debug.visual_confirm_rect_height;
}
REG_SET_2(RECOUT_START, 0,
/* First pixel of RECOUT in the active OTG area */
RECOUT_START_X, recout->x,
@@ -598,7 +613,8 @@ static void dpp1_dscl_set_recout(struct dcn10_dpp *dpp,
/* Number of RECOUT horizontal pixels */
RECOUT_WIDTH, recout->width,
/* Number of RECOUT vertical lines */
RECOUT_HEIGHT, recout->height);
RECOUT_HEIGHT, recout->height
- visual_confirm_on * 2 * (dpp->base.inst + visual_confirm_rect_height));
}
/**