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drm/msm/dpu: drop vbif_idx from WB configuration

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All MDP / DPU implementations except for MSM8996 use VBIF_RT (or the
only VBIF) for WB2. Writeback on MSM8996 is not supported (nor planned
to be supported). In order to simplify the driver, drop the field form
the struct dpu_wb_cfg.

Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Patchwork: https://patchwork.freedesktop.org/patch/707778/
Link: https://lore.kernel.org/r/20260227-drop-vbif-nrt-v1-5-2b97d0438182@oss.qualcomm.com
[DB: also handled Eliza platform]
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
This commit is contained in:
Dmitry Baryshkov
2026-02-27 20:36:44 +02:00
parent b26bfb5bf1
commit 021fd8ca0c
22 changed files with 4 additions and 24 deletions
Download Patch File Download Diff File Expand all files Collapse all files

1
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h
View File

@@ -322,7 +322,6 @@ static const struct dpu_wb_cfg sm8650_wb[] = {
.format_list = wb2_formats_rgb_yuv,
.num_formats = ARRAY_SIZE(wb2_formats_rgb_yuv),
.xin_id = 6,
.vbif_idx = VBIF_RT,
.maxlinewidth = 4096,
.intr_wb_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 4),
},

1
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_12_0_sm8750.h
View File

@@ -364,7 +364,6 @@ static const struct dpu_wb_cfg sm8750_wb[] = {
.format_list = wb2_formats_rgb_yuv,
.num_formats = ARRAY_SIZE(wb2_formats_rgb_yuv),
.xin_id = 6,
.vbif_idx = VBIF_RT,
.maxlinewidth = 4096,
.intr_wb_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 4),
},

1
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_12_2_glymur.h
View File

@@ -371,7 +371,6 @@ static const struct dpu_wb_cfg glymur_wb[] = {
.format_list = wb2_formats_rgb_yuv,
.num_formats = ARRAY_SIZE(wb2_formats_rgb_yuv),
.xin_id = 6,
.vbif_idx = VBIF_RT,
.maxlinewidth = 4096,
.intr_wb_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 4),
},

1
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_12_4_eliza.h
View File

@@ -235,7 +235,6 @@ static const struct dpu_wb_cfg eliza_wb[] = {
.format_list = wb2_formats_rgb_yuv,
.num_formats = ARRAY_SIZE(wb2_formats_rgb_yuv),
.xin_id = 6,
.vbif_idx = VBIF_RT,
.maxlinewidth = 4096,
.intr_wb_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 4),
},

1
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_13_0_kaanapali.h
View File

@@ -362,7 +362,6 @@ static const struct dpu_wb_cfg kaanapali_wb[] = {
.format_list = wb2_formats_rgb_yuv,
.num_formats = ARRAY_SIZE(wb2_formats_rgb_yuv),
.xin_id = 6,
.vbif_idx = VBIF_RT,
.maxlinewidth = 4096,
.intr_wb_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 4),
},

1
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h
View File

@@ -280,7 +280,6 @@ static const struct dpu_wb_cfg sm8150_wb[] = {
.num_formats = ARRAY_SIZE(wb2_formats_rgb_yuv),
.clk_ctrl = DPU_CLK_CTRL_WB2,
.xin_id = 6,
.vbif_idx = VBIF_RT,
.maxlinewidth = 4096,
.intr_wb_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 4),
},

1
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h
View File

@@ -286,7 +286,6 @@ static const struct dpu_wb_cfg sc8180x_wb[] = {
.num_formats = ARRAY_SIZE(wb2_formats_rgb_yuv),
.clk_ctrl = DPU_CLK_CTRL_WB2,
.xin_id = 6,
.vbif_idx = VBIF_RT,
.maxlinewidth = 4096,
.intr_wb_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 4),
},

1
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_2_sm7150.h
View File

@@ -246,7 +246,6 @@ static const struct dpu_wb_cfg sm7150_wb[] = {
.num_formats = ARRAY_SIZE(wb2_formats_rgb_yuv),
.clk_ctrl = DPU_CLK_CTRL_WB2,
.xin_id = 6,
.vbif_idx = VBIF_RT,
.maxlinewidth = 4096,
.intr_wb_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 4),
},

1
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_3_sm6150.h
View File

@@ -158,7 +158,6 @@ static const struct dpu_wb_cfg sm6150_wb[] = {
.num_formats = ARRAY_SIZE(wb2_formats_rgb_yuv),
.clk_ctrl = DPU_CLK_CTRL_WB2,
.xin_id = 6,
.vbif_idx = VBIF_RT,
.maxlinewidth = 2160,
.intr_wb_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 4),
},

1
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_4_sm6125.h
View File

@@ -137,7 +137,6 @@ static const struct dpu_wb_cfg sm6125_wb[] = {
.num_formats = ARRAY_SIZE(wb2_formats_rgb_yuv),
.clk_ctrl = DPU_CLK_CTRL_WB2,
.xin_id = 6,
.vbif_idx = VBIF_RT,
.maxlinewidth = 2160,
.intr_wb_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 4),
},

1
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h
View File

@@ -317,7 +317,6 @@ static const struct dpu_wb_cfg sm8250_wb[] = {
.num_formats = ARRAY_SIZE(wb2_formats_rgb_yuv),
.clk_ctrl = DPU_CLK_CTRL_WB2,
.xin_id = 6,
.vbif_idx = VBIF_RT,
.maxlinewidth = 4096,
.intr_wb_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 4),
},

1
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h
View File

@@ -153,7 +153,6 @@ static const struct dpu_wb_cfg sc7180_wb[] = {
.num_formats = ARRAY_SIZE(wb2_formats_rgb_yuv),
.clk_ctrl = DPU_CLK_CTRL_WB2,
.xin_id = 6,
.vbif_idx = VBIF_RT,
.maxlinewidth = 4096,
.intr_wb_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 4),
},

1
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h
View File

@@ -147,7 +147,6 @@ static const struct dpu_wb_cfg sm6350_wb[] = {
.num_formats = ARRAY_SIZE(wb2_formats_rgb_yuv),
.clk_ctrl = DPU_CLK_CTRL_WB2,
.xin_id = 6,
.vbif_idx = VBIF_RT,
.maxlinewidth = 1920,
.intr_wb_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 4),
},

1
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h
View File

@@ -290,7 +290,6 @@ static const struct dpu_wb_cfg sm8350_wb[] = {
.num_formats = ARRAY_SIZE(wb2_formats_rgb_yuv),
.clk_ctrl = DPU_CLK_CTRL_WB2,
.xin_id = 6,
.vbif_idx = VBIF_RT,
.maxlinewidth = 4096,
.intr_wb_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 4),
},

1
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h
View File

@@ -172,7 +172,6 @@ static const struct dpu_wb_cfg sc7280_wb[] = {
.num_formats = ARRAY_SIZE(wb2_formats_rgb_yuv),
.clk_ctrl = DPU_CLK_CTRL_WB2,
.xin_id = 6,
.vbif_idx = VBIF_RT,
.maxlinewidth = 4096,
.intr_wb_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 4),
},

1
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h
View File

@@ -303,7 +303,6 @@ static const struct dpu_wb_cfg sm8450_wb[] = {
.num_formats = ARRAY_SIZE(wb2_formats_rgb_yuv),
.clk_ctrl = DPU_CLK_CTRL_WB2,
.xin_id = 6,
.vbif_idx = VBIF_RT,
.maxlinewidth = 4096,
.intr_wb_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 4),
},

1
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_4_sa8775p.h
View File

@@ -310,7 +310,6 @@ static const struct dpu_wb_cfg sa8775p_wb[] = {
.num_formats = ARRAY_SIZE(wb2_formats_rgb_yuv),
.clk_ctrl = DPU_CLK_CTRL_WB2,
.xin_id = 6,
.vbif_idx = VBIF_RT,
.maxlinewidth = 4096,
.intr_wb_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 4),
},

1
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h
View File

@@ -298,7 +298,6 @@ static const struct dpu_wb_cfg sm8550_wb[] = {
.format_list = wb2_formats_rgb_yuv,
.num_formats = ARRAY_SIZE(wb2_formats_rgb_yuv),
.xin_id = 6,
.vbif_idx = VBIF_RT,
.maxlinewidth = 4096,
.intr_wb_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 4),
},

1
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_1_sar2130p.h
View File

@@ -298,7 +298,6 @@ static const struct dpu_wb_cfg sar2130p_wb[] = {
.format_list = wb2_formats_rgb_yuv,
.num_formats = ARRAY_SIZE(wb2_formats_rgb_yuv),
.xin_id = 6,
.vbif_idx = VBIF_RT,
.maxlinewidth = 4096,
.intr_wb_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 4),
},

1
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_2_x1e80100.h
View File

@@ -298,7 +298,6 @@ static const struct dpu_wb_cfg x1e80100_wb[] = {
.format_list = wb2_formats_rgb_yuv,
.num_formats = ARRAY_SIZE(wb2_formats_rgb_yuv),
.xin_id = 6,
.vbif_idx = VBIF_RT,
.maxlinewidth = 4096,
.intr_wb_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 4),
},

6
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c
View File

@@ -70,7 +70,8 @@ static void dpu_encoder_phys_wb_set_ot_limit(
ot_params.height = phys_enc->cached_mode.vdisplay;
ot_params.is_wfd = !dpu_encoder_helper_get_cwb_mask(phys_enc);
ot_params.frame_rate = drm_mode_vrefresh(&phys_enc->cached_mode);
ot_params.vbif_idx = hw_wb->caps->vbif_idx;
/* XXX: WB on MSM8996 should use VBIF_NRT */
ot_params.vbif_idx = VBIF_RT;
ot_params.rd = false;
if (!_dpu_encoder_phys_wb_clk_force_ctrl(hw_wb, phys_enc->dpu_kms->hw_mdp,
@@ -108,7 +109,8 @@ static void dpu_encoder_phys_wb_set_qos_remap(
hw_wb = phys_enc->hw_wb;
memset(&qos_params, 0, sizeof(qos_params));
qos_params.vbif_idx = hw_wb->caps->vbif_idx;
/* XXX: WB on MSM8996 should use VBIF_NRT */
qos_params.vbif_idx = VBIF_RT;
qos_params.xin_id = hw_wb->caps->xin_id;
qos_params.num = hw_wb->idx - WB_0;
qos_params.is_rt = dpu_encoder_helper_get_cwb_mask(phys_enc);

2
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
View File

@@ -524,7 +524,6 @@ struct dpu_intf_cfg {
/**
* struct dpu_wb_cfg - information of writeback blocks
* @DPU_HW_BLK_INFO: refer to the description above for DPU_HW_BLK_INFO
* @vbif_idx: vbif client index
* @maxlinewidth: max line width supported by writeback block
* @xin_id: bus client identifier
* @intr_wb_done: interrupt index for WB_DONE
@@ -535,7 +534,6 @@ struct dpu_intf_cfg {
struct dpu_wb_cfg {
DPU_HW_BLK_INFO;
unsigned long features;
u8 vbif_idx;
u32 maxlinewidth;
u32 xin_id;
unsigned int intr_wb_done;