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arm64: dts: imx8qxp-mek: support wcpu board's wm8962 codec

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The i.MX8QXP WCPU MEK board is a reworked version of the i.MX8QXP MEK
board, which includes some sensor and component changes. One of these
components is the WM8962 codec, which is meant to replace the WM8960
codec present on i.MX8QXP MEK. To avoid having to introduce a devicetree
overlay or another DTS, the WM8962 can be supported by using a virtual
I2C MUX since both of the codecs share the same I2C address.

Signed-off-by: Laurentiu Mihalcea <laurentiu.mihalcea@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
This commit is contained in:
Laurentiu Mihalcea
2025-06-17 10:52:19 -04:00
committed by Shawn Guo
parent 3522ec076f
commit 0216cffc4f
1 changed files with 80 additions and 23 deletions
Download Patch File Download Diff File Expand all files Collapse all files

103
arch/arm64/boot/dts/freescale/imx8qxp-mek.dts
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@@ -64,6 +64,71 @@ usb3_data_ss: endpoint {
};
};
i2c-mux {
compatible = "i2c-mux-gpio";
mux-gpios = <&lsio_gpio5 0 GPIO_ACTIVE_HIGH>; /* needs to be an unused GPIO */
i2c-parent = <&cm40_i2c>;
#address-cells = <1>;
#size-cells = <0>;
i2c@0 {
reg = <0>;
#address-cells = <1>;
#size-cells = <0>;
wm8960: audio-codec@1a {
compatible = "wlf,wm8960";
reg = <0x1a>;
clocks = <&mclkout0_lpcg IMX_LPCG_CLK_0>;
clock-names = "mclk";
assigned-clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>,
<&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>,
<&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>,
<&mclkout0_lpcg IMX_LPCG_CLK_0>;
assigned-clock-rates = <786432000>,
<49152000>,
<12288000>,
<12288000>;
wlf,shared-lrclk;
wlf,hp-cfg = <2 2 3>;
wlf,gpio-cfg = <1 3>;
AVDD-supply = <&reg_audio_3v3>;
DBVDD-supply = <&reg_audio_1v8>;
DCVDD-supply = <&reg_audio_1v8>;
SPKVDD1-supply = <&reg_audio_5v>;
SPKVDD2-supply = <&reg_audio_5v>;
};
};
i2c@1 {
reg = <1>;
#address-cells = <1>;
#size-cells = <0>;
wm8962: wm8962@1a {
compatible = "wlf,wm8962";
reg = <0x1a>;
clocks = <&mclkout0_lpcg IMX_LPCG_CLK_0>;
assigned-clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>,
<&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>,
<&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>,
<&mclkout0_lpcg IMX_LPCG_CLK_0>;
assigned-clock-rates = <786432000>,
<49152000>,
<12288000>,
<12288000>;
DCVDD-supply = <&reg_audio_1v8>;
DBVDD-supply = <&reg_audio_1v8>;
AVDD-supply = <&reg_audio_1v8>;
CPVDD-supply = <&reg_audio_1v8>;
MICVDD-supply = <&reg_audio_3v3>;
PLLVDD-supply = <&reg_audio_1v8>;
SPKVDD1-supply = <&reg_audio_5v>;
SPKVDD2-supply = <&reg_audio_5v>;
};
};
};
reg_pcieb: regulator-pcie {
compatible = "regulator-fixed";
regulator-max-microvolt = <3300000>;
@@ -248,6 +313,21 @@ sound-wm8960 {
"LINPUT1", "Mic Jack",
"Mic Jack", "MICB";
};
sound-wm8962 {
compatible = "fsl,imx-audio-wm8962";
model = "wm8962-audio";
audio-cpu = <&sai1>;
audio-codec = <&wm8962>;
hp-det-gpios = <&lsio_gpio1 0 GPIO_ACTIVE_HIGH>;
audio-routing = "Headphone Jack", "HPOUTL",
"Headphone Jack", "HPOUTR",
"Ext Spk", "SPKOUTL",
"Ext Spk", "SPKOUTR",
"AMIC", "MICBIAS",
"IN3R", "AMIC",
"IN1R", "AMIC";
};
};
&amix {
@@ -427,29 +507,6 @@ &cm40_i2c {
sda-gpios = <&lsio_gpio1 9 GPIO_ACTIVE_HIGH>;
status = "okay";
wm8960: audio-codec@1a {
compatible = "wlf,wm8960";
reg = <0x1a>;
clocks = <&mclkout0_lpcg IMX_LPCG_CLK_0>;
clock-names = "mclk";
assigned-clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>,
<&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>,
<&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>,
<&mclkout0_lpcg IMX_LPCG_CLK_0>;
assigned-clock-rates = <786432000>,
<49152000>,
<12288000>,
<12288000>;
wlf,shared-lrclk;
wlf,hp-cfg = <2 2 3>;
wlf,gpio-cfg = <1 3>;
AVDD-supply = <&reg_audio_3v3>;
DBVDD-supply = <&reg_audio_1v8>;
DCVDD-supply = <&reg_audio_1v8>;
SPKVDD1-supply = <&reg_audio_5v>;
SPKVDD2-supply = <&reg_audio_5v>;
};
pca6416: gpio@20 {
compatible = "ti,tca6416";
reg = <0x20>;