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riscv: dts: sophgo: Move riscv cpu definition to a separate file

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As sg2000 and sg2002 can boot from an arm a53 core, it is not
suitable to left the riscv cpu definition in the common peripheral
header.

Move the riscv related device into a separate header file, so the
arm subsystem can reuse the common peripheral header.

Signed-off-by: Alexander Sverdlin <alexander.sverdlin@gmail.com>
Link: https://lore.kernel.org/r/20250430012654.235830-3-inochiama@gmail.com
Signed-off-by: Inochi Amaoto <inochiama@gmail.com>
Signed-off-by: Chen Wang <unicorn_wang@outlook.com>
Signed-off-by: Chen Wang <wangchen20@iscas.ac.cn>
This commit is contained in:
Inochi Amaoto
2025-04-30 09:26:51 +08:00
parent 33da812c45
commit 0212bd4fad
5 changed files with 39 additions and 29 deletions
Download Patch File Download Diff File Expand all files Collapse all files

1
arch/riscv/boot/dts/sophgo/cv1800b.dtsi
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@@ -4,6 +4,7 @@
*/
#include <dt-bindings/pinctrl/pinctrl-cv1800b.h>
#include "cv180x-cpus.dtsi"
#include "cv18xx.dtsi"
/ {

36
arch/riscv/boot/dts/sophgo/cv180x-cpus.dtsi Normal file
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@@ -0,0 +1,36 @@
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
* Copyright (C) 2023 Jisheng Zhang <jszhang@kernel.org>
* Copyright (C) 2023 Inochi Amaoto <inochiama@outlook.com>
*/
/ {
cpus: cpus {
#address-cells = <1>;
#size-cells = <0>;
timebase-frequency = <25000000>;
cpu0: cpu@0 {
compatible = "thead,c906", "riscv";
device_type = "cpu";
reg = <0>;
d-cache-block-size = <64>;
d-cache-sets = <512>;
d-cache-size = <65536>;
i-cache-block-size = <64>;
i-cache-sets = <128>;
i-cache-size = <32768>;
mmu-type = "riscv,sv39";
riscv,isa = "rv64imafdc";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
"zifencei", "zihpm";
cpu0_intc: interrupt-controller {
compatible = "riscv,cpu-intc";
interrupt-controller;
#interrupt-cells = <1>;
};
};
};
};

1
arch/riscv/boot/dts/sophgo/cv1812h.dtsi
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@@ -5,6 +5,7 @@
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/pinctrl/pinctrl-cv1812h.h>
#include "cv180x-cpus.dtsi"
#include "cv18xx.dtsi"
#include "cv181x.dtsi"

29
arch/riscv/boot/dts/sophgo/cv18xx.dtsi
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@@ -12,35 +12,6 @@ / {
#address-cells = <1>;
#size-cells = <1>;
cpus: cpus {
#address-cells = <1>;
#size-cells = <0>;
timebase-frequency = <25000000>;
cpu0: cpu@0 {
compatible = "thead,c906", "riscv";
device_type = "cpu";
reg = <0>;
d-cache-block-size = <64>;
d-cache-sets = <512>;
d-cache-size = <65536>;
i-cache-block-size = <64>;
i-cache-sets = <128>;
i-cache-size = <32768>;
mmu-type = "riscv,sv39";
riscv,isa = "rv64imafdc";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
"zifencei", "zihpm";
cpu0_intc: interrupt-controller {
compatible = "riscv,cpu-intc";
interrupt-controller;
#interrupt-cells = <1>;
};
};
};
osc: oscillator {
compatible = "fixed-clock";
clock-output-names = "osc_25m";

1
arch/riscv/boot/dts/sophgo/sg2002.dtsi
View File

@@ -5,6 +5,7 @@
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/pinctrl/pinctrl-sg2002.h>
#include "cv180x-cpus.dtsi"
#include "cv18xx.dtsi"
#include "cv181x.dtsi"