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Merge tag 'renesas-dts-for-v6.12-tag1' of https://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel into soc/dt

Browse Source 
Renesas DTS updates for v6.12

  - Add support for sound, push switches, and GP LEDs on the Gray Hawk
    Single development board,
  - Add missing iommus properties on R-Car Gen3/Gen4 and RZ/G2 SoCs,
  - Add PWM support for the R-Car V4M SoC,
  - Improve Ethernet descriptions on the RZ/G2L, RZ/G2LC, and RZ/G2UL
    SMARC SoMs,
  - Add DMAC support for the RZ/G3S SoC,
  - Add CAN-FD support for the R-Car V4M SoC and the Gray Hawk Single
    development board.

* tag 'renesas-dts-for-v6.12-tag1' of https://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel: (25 commits)
  arm64: dts: renesas: gray-hawk-single: Add CAN-FD support
  arm64: dts: renesas: r8a779h0: Add CAN-FD node
  arm64: dts: renesas: r9a08g045: Add DMAC node
  arm64: dts: renesas: rzg2ul: Set Ethernet PVDD to 1.8V
  arm64: dts: renesas: rzg2lc: Set Ethernet PVDD to 1.8V
  arm64: dts: renesas: rzg2l: Set Ethernet PVDD to 1.8V
  arm64: dts: renesas: rzg2ul: Enable Ethernet TXC output
  arm64: dts: renesas: rzg2lc: Enable Ethernet TXC output
  arm64: dts: renesas: rzg2l: Enable Ethernet TXC output
  arm64: dts: renesas: r8a779h0: Add PWM device nodes
  arm64: dts: renesas: gray-hawk-single: Add GP LEDs
  arm64: dts: renesas: gray-hawk-single: Add push switches
  arm64: dts: renesas: r8a779h0: Add missing iommus properties
  arm64: dts: renesas: r8a779g0: Add missing iommus properties
  arm64: dts: renesas: r8a779a0: Add missing iommus properties
  arm64: dts: renesas: r8a77980: Add missing iommus properties
  arm64: dts: renesas: r8a77970: Add missing iommus property
  arm64: dts: renesas: r8a77965: Add missing iommus properties
  arm64: dts: renesas: r8a77961: Add missing iommus properties
  arm64: dts: renesas: r8a77960: Add missing iommus properties
  ...

Link: https://lore.kernel.org/r/cover.1724316485.git.geert+renesas@glider.be
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann
2024-09-03 10:28:40 +00:00
parent ca947a4b03 ab7d885a33
commit 01dc1baee8
17 changed files with 575 additions and 80 deletions
Download Patch File Download Diff File Expand all files Collapse all files

6
arch/arm64/boot/dts/renesas/r8a774a1.dtsi
View File

@@ -2277,6 +2277,7 @@ sdhi0: mmc@ee100000 {
max-frequency = <200000000>;
power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
resets = <&cpg 314>;
iommus = <&ipmmu_ds1 32>;
status = "disabled";
};
@@ -2290,6 +2291,7 @@ sdhi1: mmc@ee120000 {
max-frequency = <200000000>;
power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
resets = <&cpg 313>;
iommus = <&ipmmu_ds1 33>;
status = "disabled";
};
@@ -2303,6 +2305,7 @@ sdhi2: mmc@ee140000 {
max-frequency = <200000000>;
power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
resets = <&cpg 312>;
iommus = <&ipmmu_ds1 34>;
status = "disabled";
};
@@ -2316,6 +2319,7 @@ sdhi3: mmc@ee160000 {
max-frequency = <200000000>;
power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
resets = <&cpg 311>;
iommus = <&ipmmu_ds1 35>;
status = "disabled";
};
@@ -2464,6 +2468,7 @@ fcpf0: fcp@fe950000 {
clocks = <&cpg CPG_MOD 615>;
power-domains = <&sysc R8A774A1_PD_A3VC>;
resets = <&cpg 615>;
iommus = <&ipmmu_vc0 16>;
};
fcpvb0: fcp@fe96f000 {
@@ -2472,6 +2477,7 @@ fcpvb0: fcp@fe96f000 {
clocks = <&cpg CPG_MOD 607>;
power-domains = <&sysc R8A774A1_PD_A3VC>;
resets = <&cpg 607>;
iommus = <&ipmmu_vi0 5>;
};
fcpvd0: fcp@fea27000 {

26
arch/arm64/boot/dts/renesas/r8a774b1.dtsi
View File

@@ -2004,6 +2004,14 @@ audma0: dma-controller@ec700000 {
resets = <&cpg 502>;
#dma-cells = <1>;
dma-channels = <16>;
iommus = <&ipmmu_mp 0>, <&ipmmu_mp 1>,
<&ipmmu_mp 2>, <&ipmmu_mp 3>,
<&ipmmu_mp 4>, <&ipmmu_mp 5>,
<&ipmmu_mp 6>, <&ipmmu_mp 7>,
<&ipmmu_mp 8>, <&ipmmu_mp 9>,
<&ipmmu_mp 10>, <&ipmmu_mp 11>,
<&ipmmu_mp 12>, <&ipmmu_mp 13>,
<&ipmmu_mp 14>, <&ipmmu_mp 15>;
};
audma1: dma-controller@ec720000 {
@@ -2038,6 +2046,14 @@ audma1: dma-controller@ec720000 {
resets = <&cpg 501>;
#dma-cells = <1>;
dma-channels = <16>;
iommus = <&ipmmu_mp 16>, <&ipmmu_mp 17>,
<&ipmmu_mp 18>, <&ipmmu_mp 19>,
<&ipmmu_mp 20>, <&ipmmu_mp 21>,
<&ipmmu_mp 22>, <&ipmmu_mp 23>,
<&ipmmu_mp 24>, <&ipmmu_mp 25>,
<&ipmmu_mp 26>, <&ipmmu_mp 27>,
<&ipmmu_mp 28>, <&ipmmu_mp 29>,
<&ipmmu_mp 30>, <&ipmmu_mp 31>;
};
xhci0: usb@ee000000 {
@@ -2145,6 +2161,7 @@ sdhi0: mmc@ee100000 {
max-frequency = <200000000>;
power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
resets = <&cpg 314>;
iommus = <&ipmmu_ds1 32>;
status = "disabled";
};
@@ -2158,6 +2175,7 @@ sdhi1: mmc@ee120000 {
max-frequency = <200000000>;
power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
resets = <&cpg 313>;
iommus = <&ipmmu_ds1 33>;
status = "disabled";
};
@@ -2171,6 +2189,7 @@ sdhi2: mmc@ee140000 {
max-frequency = <200000000>;
power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
resets = <&cpg 312>;
iommus = <&ipmmu_ds1 34>;
status = "disabled";
};
@@ -2184,6 +2203,7 @@ sdhi3: mmc@ee160000 {
max-frequency = <200000000>;
power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
resets = <&cpg 311>;
iommus = <&ipmmu_ds1 35>;
status = "disabled";
};
@@ -2211,6 +2231,7 @@ sata: sata@ee300000 {
clocks = <&cpg CPG_MOD 815>;
power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
resets = <&cpg 815>;
iommus = <&ipmmu_hc 2>;
status = "disabled";
};
@@ -2343,6 +2364,7 @@ fcpf0: fcp@fe950000 {
clocks = <&cpg CPG_MOD 615>;
power-domains = <&sysc R8A774B1_PD_A3VP>;
resets = <&cpg 615>;
iommus = <&ipmmu_vp0 0>;
};
vspb: vsp@fe960000 {
@@ -2395,6 +2417,7 @@ fcpvb0: fcp@fe96f000 {
clocks = <&cpg CPG_MOD 607>;
power-domains = <&sysc R8A774B1_PD_A3VP>;
resets = <&cpg 607>;
iommus = <&ipmmu_vp0 5>;
};
fcpvd0: fcp@fea27000 {
@@ -2403,6 +2426,7 @@ fcpvd0: fcp@fea27000 {
clocks = <&cpg CPG_MOD 603>;
power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
resets = <&cpg 603>;
iommus = <&ipmmu_vi0 8>;
};
fcpvd1: fcp@fea2f000 {
@@ -2411,6 +2435,7 @@ fcpvd1: fcp@fea2f000 {
clocks = <&cpg CPG_MOD 602>;
power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
resets = <&cpg 602>;
iommus = <&ipmmu_vi0 9>;
};
fcpvi0: fcp@fe9af000 {
@@ -2419,6 +2444,7 @@ fcpvi0: fcp@fe9af000 {
clocks = <&cpg CPG_MOD 611>;
power-domains = <&sysc R8A774B1_PD_A3VP>;
resets = <&cpg 611>;
iommus = <&ipmmu_vp0 8>;
};
csi20: csi2@fea80000 {

3
arch/arm64/boot/dts/renesas/r8a774c0.dtsi
View File

@@ -1637,6 +1637,7 @@ sdhi0: mmc@ee100000 {
max-frequency = <200000000>;
power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
resets = <&cpg 314>;
iommus = <&ipmmu_ds1 32>;
status = "disabled";
};
@@ -1650,6 +1651,7 @@ sdhi1: mmc@ee120000 {
max-frequency = <200000000>;
power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
resets = <&cpg 313>;
iommus = <&ipmmu_ds1 33>;
status = "disabled";
};
@@ -1663,6 +1665,7 @@ sdhi3: mmc@ee160000 {
max-frequency = <200000000>;
power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
resets = <&cpg 311>;
iommus = <&ipmmu_ds1 35>;
status = "disabled";
};

8
arch/arm64/boot/dts/renesas/r8a774e1.dtsi
View File

@@ -2652,6 +2652,7 @@ fcpf0: fcp@fe950000 {
clocks = <&cpg CPG_MOD 615>;
power-domains = <&sysc R8A774E1_PD_A3VP>;
resets = <&cpg 615>;
iommus = <&ipmmu_vp0 0>;
};
fcpf1: fcp@fe951000 {
@@ -2660,6 +2661,7 @@ fcpf1: fcp@fe951000 {
clocks = <&cpg CPG_MOD 614>;
power-domains = <&sysc R8A774E1_PD_A3VP>;
resets = <&cpg 614>;
iommus = <&ipmmu_vp1 1>;
};
fcpvb0: fcp@fe96f000 {
@@ -2668,6 +2670,7 @@ fcpvb0: fcp@fe96f000 {
clocks = <&cpg CPG_MOD 607>;
power-domains = <&sysc R8A774E1_PD_A3VP>;
resets = <&cpg 607>;
iommus = <&ipmmu_vp0 5>;
};
fcpvb1: fcp@fe92f000 {
@@ -2676,6 +2679,7 @@ fcpvb1: fcp@fe92f000 {
clocks = <&cpg CPG_MOD 606>;
power-domains = <&sysc R8A774E1_PD_A3VP>;
resets = <&cpg 606>;
iommus = <&ipmmu_vp1 7>;
};
fcpvi0: fcp@fe9af000 {
@@ -2684,6 +2688,7 @@ fcpvi0: fcp@fe9af000 {
clocks = <&cpg CPG_MOD 611>;
power-domains = <&sysc R8A774E1_PD_A3VP>;
resets = <&cpg 611>;
iommus = <&ipmmu_vp0 8>;
};
fcpvi1: fcp@fe9bf000 {
@@ -2692,6 +2697,7 @@ fcpvi1: fcp@fe9bf000 {
clocks = <&cpg CPG_MOD 610>;
power-domains = <&sysc R8A774E1_PD_A3VP>;
resets = <&cpg 610>;
iommus = <&ipmmu_vp1 9>;
};
fcpvd0: fcp@fea27000 {
@@ -2700,6 +2706,7 @@ fcpvd0: fcp@fea27000 {
clocks = <&cpg CPG_MOD 603>;
power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
resets = <&cpg 603>;
iommus = <&ipmmu_vi0 8>;
};
fcpvd1: fcp@fea2f000 {
@@ -2708,6 +2715,7 @@ fcpvd1: fcp@fea2f000 {
clocks = <&cpg CPG_MOD 602>;
power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
resets = <&cpg 602>;
iommus = <&ipmmu_vi0 9>;
};
csi20: csi2@fea80000 {

2
arch/arm64/boot/dts/renesas/r8a77960.dtsi
View File

@@ -2652,6 +2652,7 @@ fcpf0: fcp@fe950000 {
clocks = <&cpg CPG_MOD 615>;
power-domains = <&sysc R8A7796_PD_A3VC>;
resets = <&cpg 615>;
iommus = <&ipmmu_vc0 16>;
};
fcpvb0: fcp@fe96f000 {
@@ -2660,6 +2661,7 @@ fcpvb0: fcp@fe96f000 {
clocks = <&cpg CPG_MOD 607>;
power-domains = <&sysc R8A7796_PD_A3VC>;
resets = <&cpg 607>;
iommus = <&ipmmu_vi0 5>;
};
fcpvi0: fcp@fe9af000 {

2
arch/arm64/boot/dts/renesas/r8a77961.dtsi
View File

@@ -2502,6 +2502,7 @@ fcpf0: fcp@fe950000 {
clocks = <&cpg CPG_MOD 615>;
power-domains = <&sysc R8A77961_PD_A3VC>;
resets = <&cpg 615>;
iommus = <&ipmmu_vc0 16>;
};
fcpvb0: fcp@fe96f000 {
@@ -2510,6 +2511,7 @@ fcpvb0: fcp@fe96f000 {
clocks = <&cpg CPG_MOD 607>;
power-domains = <&sysc R8A77961_PD_A3VC>;
resets = <&cpg 607>;
iommus = <&ipmmu_vi0 5>;
};
fcpvi0: fcp@fe9af000 {

22
arch/arm64/boot/dts/renesas/r8a77965.dtsi
View File

@@ -2185,6 +2185,14 @@ audma0: dma-controller@ec700000 {
resets = <&cpg 502>;
#dma-cells = <1>;
dma-channels = <16>;
iommus = <&ipmmu_mp 0>, <&ipmmu_mp 1>,
<&ipmmu_mp 2>, <&ipmmu_mp 3>,
<&ipmmu_mp 4>, <&ipmmu_mp 5>,
<&ipmmu_mp 6>, <&ipmmu_mp 7>,
<&ipmmu_mp 8>, <&ipmmu_mp 9>,
<&ipmmu_mp 10>, <&ipmmu_mp 11>,
<&ipmmu_mp 12>, <&ipmmu_mp 13>,
<&ipmmu_mp 14>, <&ipmmu_mp 15>;
};
audma1: dma-controller@ec720000 {
@@ -2219,6 +2227,14 @@ audma1: dma-controller@ec720000 {
resets = <&cpg 501>;
#dma-cells = <1>;
dma-channels = <16>;
iommus = <&ipmmu_mp 16>, <&ipmmu_mp 17>,
<&ipmmu_mp 18>, <&ipmmu_mp 19>,
<&ipmmu_mp 20>, <&ipmmu_mp 21>,
<&ipmmu_mp 22>, <&ipmmu_mp 23>,
<&ipmmu_mp 24>, <&ipmmu_mp 25>,
<&ipmmu_mp 26>, <&ipmmu_mp 27>,
<&ipmmu_mp 28>, <&ipmmu_mp 29>,
<&ipmmu_mp 30>, <&ipmmu_mp 31>;
};
xhci0: usb@ee000000 {
@@ -2396,6 +2412,7 @@ sata: sata@ee300000 {
clocks = <&cpg CPG_MOD 815>;
power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
resets = <&cpg 815>;
iommus = <&ipmmu_hc 2>;
status = "disabled";
};
@@ -2490,6 +2507,7 @@ fcpf0: fcp@fe950000 {
clocks = <&cpg CPG_MOD 615>;
power-domains = <&sysc R8A77965_PD_A3VP>;
resets = <&cpg 615>;
iommus = <&ipmmu_vp0 0>;
};
vspb: vsp@fe960000 {
@@ -2542,6 +2560,7 @@ fcpvb0: fcp@fe96f000 {
clocks = <&cpg CPG_MOD 607>;
power-domains = <&sysc R8A77965_PD_A3VP>;
resets = <&cpg 607>;
iommus = <&ipmmu_vp0 5>;
};
fcpvd0: fcp@fea27000 {
@@ -2550,6 +2569,7 @@ fcpvd0: fcp@fea27000 {
clocks = <&cpg CPG_MOD 603>;
power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
resets = <&cpg 603>;
iommus = <&ipmmu_vi0 8>;
};
fcpvd1: fcp@fea2f000 {
@@ -2558,6 +2578,7 @@ fcpvd1: fcp@fea2f000 {
clocks = <&cpg CPG_MOD 602>;
power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
resets = <&cpg 602>;
iommus = <&ipmmu_vi0 9>;
};
fcpvi0: fcp@fe9af000 {
@@ -2566,6 +2587,7 @@ fcpvi0: fcp@fe9af000 {
clocks = <&cpg CPG_MOD 611>;
power-domains = <&sysc R8A77965_PD_A3VP>;
resets = <&cpg 611>;
iommus = <&ipmmu_vp0 8>;
};
cmm0: cmm@fea40000 {

1
arch/arm64/boot/dts/renesas/r8a77970.dtsi
View File

@@ -1092,6 +1092,7 @@ fcpvd0: fcp@fea27000 {
clocks = <&cpg CPG_MOD 603>;
power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
resets = <&cpg 603>;
iommus = <&ipmmu_vi0 8>;
};
csi40: csi2@feaa0000 {

2
arch/arm64/boot/dts/renesas/r8a77980.dtsi
View File

@@ -1266,6 +1266,7 @@ gether: ethernet@e7400000 {
clocks = <&cpg CPG_MOD 813>;
power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
resets = <&cpg 813>;
iommus = <&ipmmu_ds1 34>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
@@ -1430,6 +1431,7 @@ fcpvd0: fcp@fea27000 {
clocks = <&cpg CPG_MOD 603>;
power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
resets = <&cpg 603>;
iommus = <&ipmmu_vi0 8>;
};
csi40: csi2@feaa0000 {

20
arch/arm64/boot/dts/renesas/r8a779a0.dtsi
View File

@@ -707,6 +707,7 @@ avb0: ethernet@e6800000 {
phy-mode = "rgmii";
rx-internal-delay-ps = <0>;
tx-internal-delay-ps = <0>;
iommus = <&ipmmu_ds1 0>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
@@ -755,6 +756,7 @@ avb1: ethernet@e6810000 {
phy-mode = "rgmii";
rx-internal-delay-ps = <0>;
tx-internal-delay-ps = <0>;
iommus = <&ipmmu_ds1 1>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
@@ -803,6 +805,7 @@ avb2: ethernet@e6820000 {
phy-mode = "rgmii";
rx-internal-delay-ps = <0>;
tx-internal-delay-ps = <0>;
iommus = <&ipmmu_ds1 2>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
@@ -851,6 +854,7 @@ avb3: ethernet@e6830000 {
phy-mode = "rgmii";
rx-internal-delay-ps = <0>;
tx-internal-delay-ps = <0>;
iommus = <&ipmmu_ds1 3>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
@@ -899,6 +903,7 @@ avb4: ethernet@e6840000 {
phy-mode = "rgmii";
rx-internal-delay-ps = <0>;
tx-internal-delay-ps = <0>;
iommus = <&ipmmu_ds1 4>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
@@ -947,6 +952,7 @@ avb5: ethernet@e6850000 {
phy-mode = "rgmii";
rx-internal-delay-ps = <0>;
tx-internal-delay-ps = <0>;
iommus = <&ipmmu_ds1 11>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
@@ -2096,6 +2102,14 @@ dmac1: dma-controller@e7350000 {
resets = <&cpg 709>;
#dma-cells = <1>;
dma-channels = <16>;
iommus = <&ipmmu_ds0 0>, <&ipmmu_ds0 1>,
<&ipmmu_ds0 2>, <&ipmmu_ds0 3>,
<&ipmmu_ds0 4>, <&ipmmu_ds0 5>,
<&ipmmu_ds0 6>, <&ipmmu_ds0 7>,
<&ipmmu_ds0 8>, <&ipmmu_ds0 9>,
<&ipmmu_ds0 10>, <&ipmmu_ds0 11>,
<&ipmmu_ds0 12>, <&ipmmu_ds0 13>,
<&ipmmu_ds0 14>, <&ipmmu_ds0 15>;
};
dmac2: dma-controller@e7351000 {
@@ -2121,6 +2135,10 @@ dmac2: dma-controller@e7351000 {
resets = <&cpg 710>;
#dma-cells = <1>;
dma-channels = <8>;
iommus = <&ipmmu_ds0 16>, <&ipmmu_ds0 17>,
<&ipmmu_ds0 18>, <&ipmmu_ds0 19>,
<&ipmmu_ds0 20>, <&ipmmu_ds0 21>,
<&ipmmu_ds0 22>, <&ipmmu_ds0 23>;
};
mmc0: mmc@ee140000 {
@@ -2278,6 +2296,7 @@ fcpvd0: fcp@fea10000 {
clocks = <&cpg CPG_MOD 508>;
power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
resets = <&cpg 508>;
iommus = <&ipmmu_vi1 6>;
};
fcpvd1: fcp@fea11000 {
@@ -2286,6 +2305,7 @@ fcpvd1: fcp@fea11000 {
clocks = <&cpg CPG_MOD 509>;
power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
resets = <&cpg 509>;
iommus = <&ipmmu_vi1 7>;
};
vspd0: vsp@fea20000 {

5
arch/arm64/boot/dts/renesas/r8a779g0.dtsi
View File

@@ -815,6 +815,7 @@ avb0: ethernet@e6800000 {
phy-mode = "rgmii";
rx-internal-delay-ps = <0>;
tx-internal-delay-ps = <0>;
iommus = <&ipmmu_hc 0>;
status = "disabled";
};
@@ -860,6 +861,7 @@ avb1: ethernet@e6810000 {
phy-mode = "rgmii";
rx-internal-delay-ps = <0>;
tx-internal-delay-ps = <0>;
iommus = <&ipmmu_hc 1>;
status = "disabled";
};
@@ -905,6 +907,7 @@ avb2: ethernet@e6820000 {
phy-mode = "rgmii";
rx-internal-delay-ps = <0>;
tx-internal-delay-ps = <0>;
iommus = <&ipmmu_hc 2>;
status = "disabled";
};
@@ -1987,6 +1990,7 @@ fcpvd0: fcp@fea10000 {
clocks = <&cpg CPG_MOD 508>;
power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
resets = <&cpg 508>;
iommus = <&ipmmu_vi1 6>;
};
fcpvd1: fcp@fea11000 {
@@ -1995,6 +1999,7 @@ fcpvd1: fcp@fea11000 {
clocks = <&cpg CPG_MOD 509>;
power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
resets = <&cpg 509>;
iommus = <&ipmmu_vi1 7>;
};
vspd0: vsp@fea20000 {

212
arch/arm64/boot/dts/renesas/r8a779h0-gray-hawk-single.dts
View File

@@ -5,10 +5,31 @@
* Copyright (C) 2023 Renesas Electronics Corp.
* Copyright (C) 2024 Glider bv
*/
/*
* [How to use Sound]
*
* Because R-Car V4M has only 1 SSI, it cannot handle both Playback/Capture
* at the same time. You need to switch the direction which is controlled
* by the GP0_01 pin via amixer.
*
* Playback (CN9500)
* > amixer set "MUX" "Playback" // for GP0_01
* > amixer set "DAC 1" 85%
* > aplay xxx.wav
*
* Capture (CN9501)
* > amixer set "MUX" "Capture" // for GP0_01
* > amixer set "Mic 1" 80%
* > amixer set "ADC 1" on
* > amixer set 'ADC 1' 80%
* > arecord xxx hoge.wav
*/
/dts-v1/;
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/leds/common.h>
#include "r8a779h0.dtsi"
@@ -26,11 +47,74 @@ aliases {
ethernet0 = &avb0;
};
can_transceiver0: can-phy0 {
compatible = "nxp,tjr1443";
#phy-cells = <0>;
enable-gpios = <&gpio1 3 GPIO_ACTIVE_HIGH>;
max-bitrate = <5000000>;
};
chosen {
bootargs = "ignore_loglevel rw root=/dev/nfs ip=on";
stdout-path = "serial0:921600n8";
};
keys {
compatible = "gpio-keys";
pinctrl-0 = <&keys_pins>;
pinctrl-names = "default";
key-1 {
gpios = <&gpio5 0 GPIO_ACTIVE_LOW>;
linux,code = <KEY_1>;
label = "SW47";
wakeup-source;
debounce-interval = <20>;
};
key-2 {
gpios = <&gpio5 1 GPIO_ACTIVE_LOW>;
linux,code = <KEY_2>;
label = "SW48";
wakeup-source;
debounce-interval = <20>;
};
key-3 {
gpios = <&gpio5 2 GPIO_ACTIVE_LOW>;
linux,code = <KEY_3>;
label = "SW49";
wakeup-source;
debounce-interval = <20>;
};
};
leds {
compatible = "gpio-leds";
led-1 {
gpios = <&gpio7 0 GPIO_ACTIVE_HIGH>;
color = <LED_COLOR_ID_GREEN>;
function = LED_FUNCTION_INDICATOR;
function-enumerator = <1>;
};
led-2 {
gpios = <&gpio7 1 GPIO_ACTIVE_HIGH>;
color = <LED_COLOR_ID_GREEN>;
function = LED_FUNCTION_INDICATOR;
function-enumerator = <2>;
};
led-3 {
gpios = <&gpio7 2 GPIO_ACTIVE_HIGH>;
color = <LED_COLOR_ID_GREEN>;
function = LED_FUNCTION_INDICATOR;
function-enumerator = <3>;
};
};
memory@48000000 {
device_type = "memory";
/* first 128MB is reserved for secure area. */
@@ -59,6 +143,24 @@ reg_3p3v: regulator-3p3v {
regulator-boot-on;
regulator-always-on;
};
sound_mux: sound-mux {
compatible = "simple-audio-mux";
mux-gpios = <&gpio0 1 GPIO_ACTIVE_HIGH>;
state-labels = "Playback", "Capture";
};
sound_card: sound {
compatible = "audio-graph-card2";
label = "rcar-sound";
aux-devs = <&sound_mux>; // for GP0_01
links = <&rsnd_port>; // AK4619 Audio Codec
};
};
&audio_clkin {
clock-frequency = <24576000>;
};
&avb0 {
@@ -79,6 +181,25 @@ phy0: ethernet-phy@0 {
};
};
&can_clk {
clock-frequency = <40000000>;
};
&canfd {
pinctrl-0 = <&canfd0_pins>, <&canfd1_pins>, <&can_clk_pins>;
pinctrl-names = "default";
status = "okay";
channel0 {
status = "okay";
phys = <&can_transceiver0>;
};
channel1 {
status = "okay";
};
};
&extal_clk {
clock-frequency = <16666666>;
};
@@ -87,6 +208,15 @@ &extalr_clk {
clock-frequency = <32768>;
};
&gpio1 {
audio-power-hog {
gpio-hog;
gpios = <8 GPIO_ACTIVE_HIGH>;
output-high;
line-name = "Audio-Power";
};
};
&hscif0 {
pinctrl-0 = <&hscif0_pins>;
pinctrl-names = "default";
@@ -139,6 +269,29 @@ eeprom@53 {
};
};
&i2c3 {
pinctrl-0 = <&i2c3_pins>;
pinctrl-names = "default";
status = "okay";
clock-frequency = <400000>;
codec@10 {
compatible = "asahi-kasei,ak4619";
reg = <0x10>;
clocks = <&rcar_sound>;
clock-names = "mclk";
#sound-dai-cells = <0>;
port {
ak4619_endpoint: endpoint {
remote-endpoint = <&rsnd_endpoint>;
};
};
};
};
&mmc0 {
pinctrl-0 = <&mmc_pins>;
pinctrl-1 = <&mmc_pins>;
@@ -178,6 +331,21 @@ pins_mii {
};
};
can_clk_pins: can-clk {
groups = "can_clk";
function = "can_clk";
};
canfd0_pins: canfd0 {
groups = "canfd0_data";
function = "canfd0";
};
canfd1_pins: canfd1 {
groups = "canfd1_data";
function = "canfd1";
};
hscif0_pins: hscif0 {
groups = "hscif0_data", "hscif0_ctrl";
function = "hscif0";
@@ -193,6 +361,16 @@ i2c0_pins: i2c0 {
function = "i2c0";
};
i2c3_pins: i2c3 {
groups = "i2c3";
function = "i2c3";
};
keys_pins: keys {
pins = "GP_5_0", "GP_5_1", "GP_5_2";
bias-pull-up;
};
mmc_pins: mmc {
groups = "mmc_data8", "mmc_ctrl", "mmc_ds";
function = "mmc";
@@ -213,6 +391,40 @@ scif_clk2_pins: scif-clk2 {
groups = "scif_clk2";
function = "scif_clk2";
};
sound_clk_pins: sound_clk {
groups = "audio_clkin", "audio_clkout";
function = "audio_clk";
};
sound_pins: sound {
groups = "ssi_ctrl", "ssi_data";
function = "ssi";
};
};
&rcar_sound {
pinctrl-0 = <&sound_clk_pins>, <&sound_pins>;
pinctrl-names = "default";
status = "okay";
/* audio_clkout */
clock-frequency = <12288000>;
ports {
rsnd_port: port {
rsnd_endpoint: endpoint {
remote-endpoint = <&ak4619_endpoint>;
bitclock-master;
frame-master;
/* see above [How to use Sound] */
playback = <&ssi0>;
capture = <&ssi0>;
};
};
};
};
&rpc {

93
arch/arm64/boot/dts/renesas/r8a779h0.dtsi
View File

@@ -21,6 +21,13 @@ audio_clkin: audio_clkin {
clock-frequency = <0>;
};
/* External CAN clock - to be overridden by boards that provide it */
can_clk: can-clk {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <0>;
};
cluster0_opp: opp-table-0 {
compatible = "operating-points-v2";
@@ -636,6 +643,40 @@ hscif3: serial@e66a0000 {
status = "disabled";
};
canfd: can@e6660000 {
compatible = "renesas,r8a779h0-canfd",
"renesas,rcar-gen4-canfd";
reg = <0 0xe6660000 0 0x8500>;
interrupts = <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 413 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "ch_int", "g_int";
clocks = <&cpg CPG_MOD 328>,
<&cpg CPG_CORE R8A779H0_CLK_CANFD>,
<&can_clk>;
clock-names = "fck", "canfd", "can_clk";
assigned-clocks = <&cpg CPG_CORE R8A779H0_CLK_CANFD>;
assigned-clock-rates = <80000000>;
power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>;
resets = <&cpg 328>;
status = "disabled";
channel0 {
status = "disabled";
};
channel1 {
status = "disabled";
};
channel2 {
status = "disabled";
};
channel3 {
status = "disabled";
};
};
avb0: ethernet@e6800000 {
compatible = "renesas,etheravb-r8a779h0",
"renesas,etheravb-rcar-gen4";
@@ -728,6 +769,7 @@ avb1: ethernet@e6810000 {
phy-mode = "rgmii";
rx-internal-delay-ps = <0>;
tx-internal-delay-ps = <0>;
iommus = <&ipmmu_hc 1>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
@@ -776,11 +818,62 @@ avb2: ethernet@e6820000 {
phy-mode = "rgmii";
rx-internal-delay-ps = <0>;
tx-internal-delay-ps = <0>;
iommus = <&ipmmu_hc 2>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
pwm0: pwm@e6e30000 {
compatible = "renesas,pwm-r8a779h0", "renesas,pwm-rcar";
reg = <0 0xe6e30000 0 0x10>;
#pwm-cells = <2>;
clocks = <&cpg CPG_MOD 628>;
power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>;
resets = <&cpg 628>;
status = "disabled";
};
pwm1: pwm@e6e31000 {
compatible = "renesas,pwm-r8a779h0", "renesas,pwm-rcar";
reg = <0 0xe6e31000 0 0x10>;
#pwm-cells = <2>;
clocks = <&cpg CPG_MOD 628>;
power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>;
resets = <&cpg 628>;
status = "disabled";
};
pwm2: pwm@e6e32000 {
compatible = "renesas,pwm-r8a779h0", "renesas,pwm-rcar";
reg = <0 0xe6e32000 0 0x10>;
#pwm-cells = <2>;
clocks = <&cpg CPG_MOD 628>;
power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>;
resets = <&cpg 628>;
status = "disabled";
};
pwm3: pwm@e6e33000 {
compatible = "renesas,pwm-r8a779h0", "renesas,pwm-rcar";
reg = <0 0xe6e33000 0 0x10>;
#pwm-cells = <2>;
clocks = <&cpg CPG_MOD 628>;
power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>;
resets = <&cpg 628>;
status = "disabled";
};
pwm4: pwm@e6e34000 {
compatible = "renesas,pwm-r8a779h0", "renesas,pwm-rcar";
reg = <0 0xe6e34000 0 0x10>;
#pwm-cells = <2>;
clocks = <&cpg CPG_MOD 628>;
power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>;
resets = <&cpg 628>;
status = "disabled";
};
scif0: serial@e6e60000 {
compatible = "renesas,scif-r8a779h0",
"renesas,rcar-gen4-scif", "renesas,scif";

38
arch/arm64/boot/dts/renesas/r9a08g045.dtsi
View File

@@ -181,6 +181,44 @@ irqc: interrupt-controller@11050000 {
resets = <&cpg R9A08G045_IA55_RESETN>;
};
dmac: dma-controller@11820000 {
compatible = "renesas,r9a08g045-dmac",
"renesas,rz-dmac";
reg = <0 0x11820000 0 0x10000>,
<0 0x11830000 0 0x10000>;
interrupts = <GIC_SPI 111 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 112 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 113 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 114 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 115 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 116 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 117 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 118 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 119 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 120 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 121 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 122 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 123 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 124 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 125 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 126 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 127 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "error",
"ch0", "ch1", "ch2", "ch3",
"ch4", "ch5", "ch6", "ch7",
"ch8", "ch9", "ch10", "ch11",
"ch12", "ch13", "ch14", "ch15";
clocks = <&cpg CPG_MOD R9A08G045_DMAC_ACLK>,
<&cpg CPG_MOD R9A08G045_DMAC_PCLK>;
clock-names = "main", "register";
power-domains = <&cpg>;
resets = <&cpg R9A08G045_DMAC_ARESETN>,
<&cpg R9A08G045_DMAC_RST_ASYNC>;
reset-names = "arst", "rst_async";
#dma-cells = <1>;
dma-channels = <16>;
};
sdhi0: mmc@11c00000 {
compatible = "renesas,sdhi-r9a08g045", "renesas,rzg2l-sdhi";
reg = <0x0 0x11c00000 0 0x10000>;

86
arch/arm64/boot/dts/renesas/rzg2l-smarc-som.dtsi
View File

@@ -180,41 +180,63 @@ adc_pins: adc {
};
eth0_pins: eth0 {
pinmux = <RZG2L_PORT_PINMUX(28, 1, 1)>, /* ET0_LINKSTA */
<RZG2L_PORT_PINMUX(27, 1, 1)>, /* ET0_MDC */
<RZG2L_PORT_PINMUX(28, 0, 1)>, /* ET0_MDIO */
<RZG2L_PORT_PINMUX(20, 0, 1)>, /* ET0_TXC */
<RZG2L_PORT_PINMUX(20, 1, 1)>, /* ET0_TX_CTL */
<RZG2L_PORT_PINMUX(20, 2, 1)>, /* ET0_TXD0 */
<RZG2L_PORT_PINMUX(21, 0, 1)>, /* ET0_TXD1 */
<RZG2L_PORT_PINMUX(21, 1, 1)>, /* ET0_TXD2 */
<RZG2L_PORT_PINMUX(22, 0, 1)>, /* ET0_TXD3 */
<RZG2L_PORT_PINMUX(24, 0, 1)>, /* ET0_RXC */
<RZG2L_PORT_PINMUX(24, 1, 1)>, /* ET0_RX_CTL */
<RZG2L_PORT_PINMUX(25, 0, 1)>, /* ET0_RXD0 */
<RZG2L_PORT_PINMUX(25, 1, 1)>, /* ET0_RXD1 */
<RZG2L_PORT_PINMUX(26, 0, 1)>, /* ET0_RXD2 */
<RZG2L_PORT_PINMUX(26, 1, 1)>, /* ET0_RXD3 */
<RZG2L_PORT_PINMUX(1, 0, 1)>; /* IRQ2 */
txc {
pinmux = <RZG2L_PORT_PINMUX(20, 0, 1)>; /* ET0_TXC */
power-source = <1800>;
output-enable;
};
mux {
pinmux = <RZG2L_PORT_PINMUX(28, 1, 1)>, /* ET0_LINKSTA */
<RZG2L_PORT_PINMUX(27, 1, 1)>, /* ET0_MDC */
<RZG2L_PORT_PINMUX(28, 0, 1)>, /* ET0_MDIO */
<RZG2L_PORT_PINMUX(20, 1, 1)>, /* ET0_TX_CTL */
<RZG2L_PORT_PINMUX(20, 2, 1)>, /* ET0_TXD0 */
<RZG2L_PORT_PINMUX(21, 0, 1)>, /* ET0_TXD1 */
<RZG2L_PORT_PINMUX(21, 1, 1)>, /* ET0_TXD2 */
<RZG2L_PORT_PINMUX(22, 0, 1)>, /* ET0_TXD3 */
<RZG2L_PORT_PINMUX(24, 0, 1)>, /* ET0_RXC */
<RZG2L_PORT_PINMUX(24, 1, 1)>, /* ET0_RX_CTL */
<RZG2L_PORT_PINMUX(25, 0, 1)>, /* ET0_RXD0 */
<RZG2L_PORT_PINMUX(25, 1, 1)>, /* ET0_RXD1 */
<RZG2L_PORT_PINMUX(26, 0, 1)>, /* ET0_RXD2 */
<RZG2L_PORT_PINMUX(26, 1, 1)>; /* ET0_RXD3 */
power-source = <1800>;
};
irq {
pinmux = <RZG2L_PORT_PINMUX(1, 0, 1)>; /* IRQ2 */
};
};
eth1_pins: eth1 {
pinmux = <RZG2L_PORT_PINMUX(37, 2, 1)>, /* ET1_LINKSTA */
<RZG2L_PORT_PINMUX(37, 0, 1)>, /* ET1_MDC */
<RZG2L_PORT_PINMUX(37, 1, 1)>, /* ET1_MDIO */
<RZG2L_PORT_PINMUX(29, 0, 1)>, /* ET1_TXC */
<RZG2L_PORT_PINMUX(29, 1, 1)>, /* ET1_TX_CTL */
<RZG2L_PORT_PINMUX(30, 0, 1)>, /* ET1_TXD0 */
<RZG2L_PORT_PINMUX(30, 1, 1)>, /* ET1_TXD1 */
<RZG2L_PORT_PINMUX(31, 0, 1)>, /* ET1_TXD2 */
<RZG2L_PORT_PINMUX(31, 1, 1)>, /* ET1_TXD3 */
<RZG2L_PORT_PINMUX(33, 1, 1)>, /* ET1_RXC */
<RZG2L_PORT_PINMUX(34, 0, 1)>, /* ET1_RX_CTL */
<RZG2L_PORT_PINMUX(34, 1, 1)>, /* ET1_RXD0 */
<RZG2L_PORT_PINMUX(35, 0, 1)>, /* ET1_RXD1 */
<RZG2L_PORT_PINMUX(35, 1, 1)>, /* ET1_RXD2 */
<RZG2L_PORT_PINMUX(36, 0, 1)>, /* ET1_RXD3 */
<RZG2L_PORT_PINMUX(1, 1, 1)>; /* IRQ3 */
txc {
pinmux = <RZG2L_PORT_PINMUX(29, 0, 1)>; /* ET1_TXC */
power-source = <1800>;
output-enable;
};
mux {
pinmux = <RZG2L_PORT_PINMUX(37, 2, 1)>, /* ET1_LINKSTA */
<RZG2L_PORT_PINMUX(37, 0, 1)>, /* ET1_MDC */
<RZG2L_PORT_PINMUX(37, 1, 1)>, /* ET1_MDIO */
<RZG2L_PORT_PINMUX(29, 1, 1)>, /* ET1_TX_CTL */
<RZG2L_PORT_PINMUX(30, 0, 1)>, /* ET1_TXD0 */
<RZG2L_PORT_PINMUX(30, 1, 1)>, /* ET1_TXD1 */
<RZG2L_PORT_PINMUX(31, 0, 1)>, /* ET1_TXD2 */
<RZG2L_PORT_PINMUX(31, 1, 1)>, /* ET1_TXD3 */
<RZG2L_PORT_PINMUX(33, 1, 1)>, /* ET1_RXC */
<RZG2L_PORT_PINMUX(34, 0, 1)>, /* ET1_RX_CTL */
<RZG2L_PORT_PINMUX(34, 1, 1)>, /* ET1_RXD0 */
<RZG2L_PORT_PINMUX(35, 0, 1)>, /* ET1_RXD1 */
<RZG2L_PORT_PINMUX(35, 1, 1)>, /* ET1_RXD2 */
<RZG2L_PORT_PINMUX(36, 0, 1)>; /* ET1_RXD3 */
power-source = <1800>;
};
irq {
pinmux = <RZG2L_PORT_PINMUX(1, 1, 1)>; /* IRQ3 */
};
};
gpio-sd0-pwr-en-hog {

43
arch/arm64/boot/dts/renesas/rzg2lc-smarc-som.dtsi
View File

@@ -128,22 +128,33 @@ &ostm2 {
&pinctrl {
eth0_pins: eth0 {
pinmux = <RZG2L_PORT_PINMUX(28, 1, 1)>, /* ET0_LINKSTA */
<RZG2L_PORT_PINMUX(27, 1, 1)>, /* ET0_MDC */
<RZG2L_PORT_PINMUX(28, 0, 1)>, /* ET0_MDIO */
<RZG2L_PORT_PINMUX(20, 0, 1)>, /* ET0_TXC */
<RZG2L_PORT_PINMUX(20, 1, 1)>, /* ET0_TX_CTL */
<RZG2L_PORT_PINMUX(20, 2, 1)>, /* ET0_TXD0 */
<RZG2L_PORT_PINMUX(21, 0, 1)>, /* ET0_TXD1 */
<RZG2L_PORT_PINMUX(21, 1, 1)>, /* ET0_TXD2 */
<RZG2L_PORT_PINMUX(22, 0, 1)>, /* ET0_TXD3 */
<RZG2L_PORT_PINMUX(24, 0, 1)>, /* ET0_RXC */
<RZG2L_PORT_PINMUX(24, 1, 1)>, /* ET0_RX_CTL */
<RZG2L_PORT_PINMUX(25, 0, 1)>, /* ET0_RXD0 */
<RZG2L_PORT_PINMUX(25, 1, 1)>, /* ET0_RXD1 */
<RZG2L_PORT_PINMUX(26, 0, 1)>, /* ET0_RXD2 */
<RZG2L_PORT_PINMUX(26, 1, 1)>, /* ET0_RXD3 */
<RZG2L_PORT_PINMUX(0, 0, 1)>; /* IRQ0 */
txc {
pinmux = <RZG2L_PORT_PINMUX(20, 0, 1)>; /* ET0_TXC */
power-source = <1800>;
output-enable;
};
mux {
pinmux = <RZG2L_PORT_PINMUX(28, 1, 1)>, /* ET0_LINKSTA */
<RZG2L_PORT_PINMUX(27, 1, 1)>, /* ET0_MDC */
<RZG2L_PORT_PINMUX(28, 0, 1)>, /* ET0_MDIO */
<RZG2L_PORT_PINMUX(20, 1, 1)>, /* ET0_TX_CTL */
<RZG2L_PORT_PINMUX(20, 2, 1)>, /* ET0_TXD0 */
<RZG2L_PORT_PINMUX(21, 0, 1)>, /* ET0_TXD1 */
<RZG2L_PORT_PINMUX(21, 1, 1)>, /* ET0_TXD2 */
<RZG2L_PORT_PINMUX(22, 0, 1)>, /* ET0_TXD3 */
<RZG2L_PORT_PINMUX(24, 0, 1)>, /* ET0_RXC */
<RZG2L_PORT_PINMUX(24, 1, 1)>, /* ET0_RX_CTL */
<RZG2L_PORT_PINMUX(25, 0, 1)>, /* ET0_RXD0 */
<RZG2L_PORT_PINMUX(25, 1, 1)>, /* ET0_RXD1 */
<RZG2L_PORT_PINMUX(26, 0, 1)>, /* ET0_RXD2 */
<RZG2L_PORT_PINMUX(26, 1, 1)>; /* ET0_RXD3 */
power-source = <1800>;
};
irq {
pinmux = <RZG2L_PORT_PINMUX(0, 0, 1)>; /* IRQ0 */
};
};
gpio-sd0-pwr-en-hog {

86
arch/arm64/boot/dts/renesas/rzg2ul-smarc-som.dtsi
View File

@@ -142,41 +142,63 @@ adc_pins: adc {
};
eth0_pins: eth0 {
pinmux = <RZG2L_PORT_PINMUX(4, 5, 1)>, /* ET0_LINKSTA */
<RZG2L_PORT_PINMUX(4, 3, 1)>, /* ET0_MDC */
<RZG2L_PORT_PINMUX(4, 4, 1)>, /* ET0_MDIO */
<RZG2L_PORT_PINMUX(1, 0, 1)>, /* ET0_TXC */
<RZG2L_PORT_PINMUX(1, 1, 1)>, /* ET0_TX_CTL */
<RZG2L_PORT_PINMUX(1, 2, 1)>, /* ET0_TXD0 */
<RZG2L_PORT_PINMUX(1, 3, 1)>, /* ET0_TXD1 */
<RZG2L_PORT_PINMUX(1, 4, 1)>, /* ET0_TXD2 */
<RZG2L_PORT_PINMUX(2, 0, 1)>, /* ET0_TXD3 */
<RZG2L_PORT_PINMUX(3, 0, 1)>, /* ET0_RXC */
<RZG2L_PORT_PINMUX(3, 1, 1)>, /* ET0_RX_CTL */
<RZG2L_PORT_PINMUX(3, 2, 1)>, /* ET0_RXD0 */
<RZG2L_PORT_PINMUX(3, 3, 1)>, /* ET0_RXD1 */
<RZG2L_PORT_PINMUX(4, 0, 1)>, /* ET0_RXD2 */
<RZG2L_PORT_PINMUX(4, 1, 1)>, /* ET0_RXD3 */
<RZG2L_PORT_PINMUX(5, 1, 7)>; /* IRQ2 */
txc {
pinmux = <RZG2L_PORT_PINMUX(1, 0, 1)>; /* ET0_TXC */
power-source = <1800>;
output-enable;
};
mux {
pinmux = <RZG2L_PORT_PINMUX(4, 5, 1)>, /* ET0_LINKSTA */
<RZG2L_PORT_PINMUX(4, 3, 1)>, /* ET0_MDC */
<RZG2L_PORT_PINMUX(4, 4, 1)>, /* ET0_MDIO */
<RZG2L_PORT_PINMUX(1, 1, 1)>, /* ET0_TX_CTL */
<RZG2L_PORT_PINMUX(1, 2, 1)>, /* ET0_TXD0 */
<RZG2L_PORT_PINMUX(1, 3, 1)>, /* ET0_TXD1 */
<RZG2L_PORT_PINMUX(1, 4, 1)>, /* ET0_TXD2 */
<RZG2L_PORT_PINMUX(2, 0, 1)>, /* ET0_TXD3 */
<RZG2L_PORT_PINMUX(3, 0, 1)>, /* ET0_RXC */
<RZG2L_PORT_PINMUX(3, 1, 1)>, /* ET0_RX_CTL */
<RZG2L_PORT_PINMUX(3, 2, 1)>, /* ET0_RXD0 */
<RZG2L_PORT_PINMUX(3, 3, 1)>, /* ET0_RXD1 */
<RZG2L_PORT_PINMUX(4, 0, 1)>, /* ET0_RXD2 */
<RZG2L_PORT_PINMUX(4, 1, 1)>; /* ET0_RXD3 */
power-source = <1800>;
};
irq {
pinmux = <RZG2L_PORT_PINMUX(5, 1, 7)>; /* IRQ2 */
};
};
eth1_pins: eth1 {
pinmux = <RZG2L_PORT_PINMUX(10, 4, 1)>, /* ET1_LINKSTA */
<RZG2L_PORT_PINMUX(10, 2, 1)>, /* ET1_MDC */
<RZG2L_PORT_PINMUX(10, 3, 1)>, /* ET1_MDIO */
<RZG2L_PORT_PINMUX(7, 0, 1)>, /* ET1_TXC */
<RZG2L_PORT_PINMUX(7, 1, 1)>, /* ET1_TX_CTL */
<RZG2L_PORT_PINMUX(7, 2, 1)>, /* ET1_TXD0 */
<RZG2L_PORT_PINMUX(7, 3, 1)>, /* ET1_TXD1 */
<RZG2L_PORT_PINMUX(7, 4, 1)>, /* ET1_TXD2 */
<RZG2L_PORT_PINMUX(8, 0, 1)>, /* ET1_TXD3 */
<RZG2L_PORT_PINMUX(8, 4, 1)>, /* ET1_RXC */
<RZG2L_PORT_PINMUX(9, 0, 1)>, /* ET1_RX_CTL */
<RZG2L_PORT_PINMUX(9, 1, 1)>, /* ET1_RXD0 */
<RZG2L_PORT_PINMUX(9, 2, 1)>, /* ET1_RXD1 */
<RZG2L_PORT_PINMUX(9, 3, 1)>, /* ET1_RXD2 */
<RZG2L_PORT_PINMUX(10, 0, 1)>, /* ET1_RXD3 */
<RZG2L_PORT_PINMUX(18, 5, 1)>; /* IRQ7 */
txc {
pinmux = <RZG2L_PORT_PINMUX(7, 0, 1)>; /* ET1_TXC */
power-source = <1800>;
output-enable;
};
mux {
pinmux = <RZG2L_PORT_PINMUX(10, 4, 1)>, /* ET1_LINKSTA */
<RZG2L_PORT_PINMUX(10, 2, 1)>, /* ET1_MDC */
<RZG2L_PORT_PINMUX(10, 3, 1)>, /* ET1_MDIO */
<RZG2L_PORT_PINMUX(7, 1, 1)>, /* ET1_TX_CTL */
<RZG2L_PORT_PINMUX(7, 2, 1)>, /* ET1_TXD0 */
<RZG2L_PORT_PINMUX(7, 3, 1)>, /* ET1_TXD1 */
<RZG2L_PORT_PINMUX(7, 4, 1)>, /* ET1_TXD2 */
<RZG2L_PORT_PINMUX(8, 0, 1)>, /* ET1_TXD3 */
<RZG2L_PORT_PINMUX(8, 4, 1)>, /* ET1_RXC */
<RZG2L_PORT_PINMUX(9, 0, 1)>, /* ET1_RX_CTL */
<RZG2L_PORT_PINMUX(9, 1, 1)>, /* ET1_RXD0 */
<RZG2L_PORT_PINMUX(9, 2, 1)>, /* ET1_RXD1 */
<RZG2L_PORT_PINMUX(9, 3, 1)>, /* ET1_RXD2 */
<RZG2L_PORT_PINMUX(10, 0, 1)>; /* ET1_RXD3 */
power-source = <1800>;
};
irq {
pinmux = <RZG2L_PORT_PINMUX(18, 5, 1)>; /* IRQ7 */
};
};
sdhi0_emmc_pins: sd0emmc {