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arm64: dts: mediatek: mt6795: Add ARM CCI-400 node and assign to CPUs

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This SoC features an ARM CCI-400 IP: add the required node and
assign the cci control ports to the CPU cores.

Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Link: https://lore.kernel.org/r/20220609112303.117928-9-angelogioacchino.delregno@collabora.com
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
This commit is contained in:
AngeloGioacchino Del Regno
2022-06-09 13:23:01 +02:00
committed by Matthias Brugger
parent 4c400f1812
commit 01931ee600
1 changed files with 44 additions and 0 deletions
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44
arch/arm64/boot/dts/mediatek/mt6795.dtsi
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@@ -34,6 +34,7 @@ cpu0: cpu@0 {
compatible = "arm,cortex-a53";
enable-method = "psci";
reg = <0x000>;
cci-control-port = <&cci_control2>;
next-level-cache = <&l2_0>;
};
@@ -42,6 +43,7 @@ cpu1: cpu@1 {
compatible = "arm,cortex-a53";
enable-method = "psci";
reg = <0x001>;
cci-control-port = <&cci_control2>;
next-level-cache = <&l2_0>;
};
@@ -50,6 +52,7 @@ cpu2: cpu@2 {
compatible = "arm,cortex-a53";
enable-method = "psci";
reg = <0x002>;
cci-control-port = <&cci_control2>;
next-level-cache = <&l2_0>;
};
@@ -58,6 +61,7 @@ cpu3: cpu@3 {
compatible = "arm,cortex-a53";
enable-method = "psci";
reg = <0x003>;
cci-control-port = <&cci_control2>;
next-level-cache = <&l2_0>;
};
@@ -66,6 +70,7 @@ cpu4: cpu@100 {
compatible = "arm,cortex-a53";
enable-method = "psci";
reg = <0x100>;
cci-control-port = <&cci_control1>;
next-level-cache = <&l2_1>;
};
@@ -74,6 +79,7 @@ cpu5: cpu@101 {
compatible = "arm,cortex-a53";
enable-method = "psci";
reg = <0x101>;
cci-control-port = <&cci_control1>;
next-level-cache = <&l2_1>;
};
@@ -82,6 +88,7 @@ cpu6: cpu@102 {
compatible = "arm,cortex-a53";
enable-method = "psci";
reg = <0x102>;
cci-control-port = <&cci_control1>;
next-level-cache = <&l2_1>;
};
@@ -90,6 +97,7 @@ cpu7: cpu@103 {
compatible = "arm,cortex-a53";
enable-method = "psci";
reg = <0x103>;
cci-control-port = <&cci_control1>;
next-level-cache = <&l2_1>;
};
@@ -226,6 +234,42 @@ gic: interrupt-controller@10221000 {
<0 0x10226000 0 0x2000>;
};
cci: cci@10390000 {
compatible = "arm,cci-400";
#address-cells = <1>;
#size-cells = <1>;
reg = <0 0x10390000 0 0x1000>;
ranges = <0 0 0x10390000 0x10000>;
cci_control0: slave-if@1000 {
compatible = "arm,cci-400-ctrl-if";
interface-type = "ace-lite";
reg = <0x1000 0x1000>;
};
cci_control1: slave-if@4000 {
compatible = "arm,cci-400-ctrl-if";
interface-type = "ace";
reg = <0x4000 0x1000>;
};
cci_control2: slave-if@5000 {
compatible = "arm,cci-400-ctrl-if";
interface-type = "ace";
reg = <0x5000 0x1000>;
};
pmu@9000 {
compatible = "arm,cci-400-pmu,r1";
reg = <0x9000 0x5000>;
interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
};
};
uart0: serial@11002000 {
compatible = "mediatek,mt6795-uart",
"mediatek,mt6577-uart";