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synced 2026-05-07 19:49:33 -04:00
iwlwifi: Revert "iwlwifi: pcie: dynamic Tx command queue size"
This reverts commit dd05f9aab4.
Shorter TX queues support was added eventually without the
need for the parameters this patch added.
Signed-off-by: Sara Sharon <sara.sharon@intel.com>
Signed-off-by: Luca Coelho <luciano.coelho@intel.com>
This commit is contained in:
@@ -137,7 +137,6 @@ static const struct iwl_ht_params iwl_22000_ht_params = {
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.gen2 = true, \
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.nvm_type = IWL_NVM_EXT, \
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.dbgc_supported = true, \
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.tx_cmd_queue_size = 32, \
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.min_umac_error_event_table = 0x400000
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const struct iwl_cfg iwl22000_2ac_cfg_hr = {
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@@ -333,8 +333,6 @@ struct iwl_pwr_tx_backoff {
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* @gen2: 22000 and on transport operation
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* @cdb: CDB support
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* @nvm_type: see &enum iwl_nvm_type
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* @tx_cmd_queue_size: size of the cmd queue. If zero, use the same value as
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* the regular queues
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*
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* We enable the driver to be backward compatible wrt. hardware features.
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* API differences in uCode shouldn't be handled here but through TLVs
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@@ -386,7 +384,6 @@ struct iwl_cfg {
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gen2:1,
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cdb:1,
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dbgc_supported:1;
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u16 tx_cmd_queue_size;
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u8 valid_tx_ant;
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u8 valid_rx_ant;
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u8 non_shared_ant;
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@@ -244,7 +244,7 @@ int iwl_pcie_ctxt_info_init(struct iwl_trans *trans,
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ctxt_info->hcmd_cfg.cmd_queue_addr =
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cpu_to_le64(trans_pcie->txq[trans_pcie->cmd_queue]->dma_addr);
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ctxt_info->hcmd_cfg.cmd_queue_size =
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TFD_QUEUE_CB_SIZE(trans_pcie->tx_cmd_queue_size);
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TFD_QUEUE_CB_SIZE(TFD_CMD_SLOTS);
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/* allocate ucode sections in dram and set addresses */
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ret = iwl_pcie_ctxt_info_init_fw_sec(trans, fw, ctxt_info);
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@@ -383,7 +383,6 @@ struct iwl_self_init_dram {
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* @hw_init_mask: initial unmasked hw causes
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* @fh_mask: current unmasked fh causes
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* @hw_mask: current unmasked hw causes
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* @tx_cmd_queue_size: the size of the tx command queue
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*/
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struct iwl_trans_pcie {
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struct iwl_rxq *rxq;
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@@ -465,7 +464,6 @@ struct iwl_trans_pcie {
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u32 fh_mask;
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u32 hw_mask;
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cpumask_t affinity_mask[IWL_MAX_RX_HW_QUEUES];
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u16 tx_cmd_queue_size;
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};
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static inline struct iwl_trans_pcie *
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@@ -537,7 +535,6 @@ void iwl_pcie_hcmd_complete(struct iwl_trans *trans,
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void iwl_trans_pcie_reclaim(struct iwl_trans *trans, int txq_id, int ssn,
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struct sk_buff_head *skbs);
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void iwl_trans_pcie_tx_reset(struct iwl_trans *trans);
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void iwl_pcie_set_tx_cmd_queue_size(struct iwl_trans *trans);
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static inline u16 iwl_pcie_tfd_tb_get_len(struct iwl_trans *trans, void *_tfd,
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u8 idx)
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@@ -1173,8 +1173,6 @@ int iwl_pcie_gen2_tx_init(struct iwl_trans *trans)
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struct iwl_txq *cmd_queue;
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int txq_id = trans_pcie->cmd_queue, ret;
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iwl_pcie_set_tx_cmd_queue_size(trans);
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/* alloc and init the command queue */
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if (!trans_pcie->txq[txq_id]) {
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cmd_queue = kzalloc(sizeof(*cmd_queue), GFP_KERNEL);
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@@ -1183,8 +1181,7 @@ int iwl_pcie_gen2_tx_init(struct iwl_trans *trans)
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return -ENOMEM;
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}
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trans_pcie->txq[txq_id] = cmd_queue;
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ret = iwl_pcie_txq_alloc(trans, cmd_queue,
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trans_pcie->tx_cmd_queue_size, true);
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ret = iwl_pcie_txq_alloc(trans, cmd_queue, TFD_CMD_SLOTS, true);
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if (ret) {
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IWL_ERR(trans, "Tx %d queue init failed\n", txq_id);
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goto error;
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@@ -1193,8 +1190,7 @@ int iwl_pcie_gen2_tx_init(struct iwl_trans *trans)
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cmd_queue = trans_pcie->txq[txq_id];
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}
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ret = iwl_pcie_txq_init(trans, cmd_queue,
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trans_pcie->tx_cmd_queue_size, true);
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ret = iwl_pcie_txq_init(trans, cmd_queue, TFD_CMD_SLOTS, true);
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if (ret) {
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IWL_ERR(trans, "Tx %d queue alloc failed\n", txq_id);
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goto error;
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@@ -953,8 +953,7 @@ static int iwl_pcie_tx_alloc(struct iwl_trans *trans)
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txq_id++) {
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bool cmd_queue = (txq_id == trans_pcie->cmd_queue);
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slots_num = cmd_queue ? trans_pcie->tx_cmd_queue_size :
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TFD_TX_CMD_SLOTS;
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slots_num = cmd_queue ? TFD_CMD_SLOTS : TFD_TX_CMD_SLOTS;
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trans_pcie->txq[txq_id] = &trans_pcie->txq_memory[txq_id];
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ret = iwl_pcie_txq_alloc(trans, trans_pcie->txq[txq_id],
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slots_num, cmd_queue);
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@@ -973,21 +972,6 @@ static int iwl_pcie_tx_alloc(struct iwl_trans *trans)
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return ret;
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}
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void iwl_pcie_set_tx_cmd_queue_size(struct iwl_trans *trans)
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{
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struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
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int queue_size = TFD_CMD_SLOTS;
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if (trans->cfg->tx_cmd_queue_size)
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queue_size = trans->cfg->tx_cmd_queue_size;
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if (WARN_ON(!(is_power_of_2(queue_size) &&
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TFD_QUEUE_CB_SIZE(queue_size) > 0)))
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trans_pcie->tx_cmd_queue_size = TFD_CMD_SLOTS;
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else
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trans_pcie->tx_cmd_queue_size = queue_size;
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}
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int iwl_pcie_tx_init(struct iwl_trans *trans)
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{
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struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
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@@ -995,8 +979,6 @@ int iwl_pcie_tx_init(struct iwl_trans *trans)
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int txq_id, slots_num;
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bool alloc = false;
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iwl_pcie_set_tx_cmd_queue_size(trans);
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if (!trans_pcie->txq_memory) {
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ret = iwl_pcie_tx_alloc(trans);
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if (ret)
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@@ -1020,8 +1002,7 @@ int iwl_pcie_tx_init(struct iwl_trans *trans)
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txq_id++) {
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bool cmd_queue = (txq_id == trans_pcie->cmd_queue);
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slots_num = cmd_queue ? trans_pcie->tx_cmd_queue_size :
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TFD_TX_CMD_SLOTS;
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slots_num = cmd_queue ? TFD_CMD_SLOTS : TFD_TX_CMD_SLOTS;
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ret = iwl_pcie_txq_init(trans, trans_pcie->txq[txq_id],
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slots_num, cmd_queue);
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if (ret) {
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