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https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
synced 2026-05-10 13:59:45 -04:00
wifi: rtw89: fw: add H2C command to reset DMAC table for WiFi 7
Reset DMAC table, so we get expected behavior instead of random values at early stage. Signed-off-by: Ping-Ke Shih <pkshih@realtek.com> Signed-off-by: Kalle Valo <kvalo@kernel.org> Link: https://msgid.link/20240115033742.16372-7-pkshih@realtek.com
This commit is contained in:
@@ -395,7 +395,9 @@ struct rtw89_h2c_dctlinfo_ud_v2 {
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#define DCTLINFO_V2_W0_HW_EXSEQ_MACID GENMASK(14, 8)
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#define DCTLINFO_V2_W0_QOS_DATA BIT(15)
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#define DCTLINFO_V2_W0_AES_IV_L GENMASK(31, 16)
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#define DCTLINFO_V2_W0_ALL GENMASK(31, 0)
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#define DCTLINFO_V2_W1_AES_IV_H GENMASK(31, 0)
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#define DCTLINFO_V2_W1_ALL GENMASK(31, 0)
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#define DCTLINFO_V2_W2_SEQ0 GENMASK(11, 0)
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#define DCTLINFO_V2_W2_SEQ1 GENMASK(23, 12)
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#define DCTLINFO_V2_W2_AMSDU_MAX_LEN GENMASK(26, 24)
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@@ -404,11 +406,13 @@ struct rtw89_h2c_dctlinfo_ud_v2 {
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#define DCTLINFO_V2_W2_WITH_LLC BIT(29)
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#define DCTLINFO_V2_W2_NAT25_EN BIT(30)
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#define DCTLINFO_V2_W2_IS_MLD BIT(31)
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#define DCTLINFO_V2_W2_ALL GENMASK(31, 0)
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#define DCTLINFO_V2_W3_SEQ2 GENMASK(11, 0)
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#define DCTLINFO_V2_W3_SEQ3 GENMASK(23, 12)
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#define DCTLINFO_V2_W3_TGT_IND GENMASK(27, 24)
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#define DCTLINFO_V2_W3_TGT_IND_EN BIT(28)
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#define DCTLINFO_V2_W3_HTC_LB GENMASK(31, 29)
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#define DCTLINFO_V2_W3_ALL GENMASK(31, 0)
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#define DCTLINFO_V2_W4_VLAN_TAG_SEL GENMASK(7, 5)
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#define DCTLINFO_V2_W4_HTC_ORDER BIT(8)
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#define DCTLINFO_V2_W4_SEC_KEY_ID GENMASK(10, 9)
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@@ -425,24 +429,33 @@ struct rtw89_h2c_dctlinfo_ud_v2 {
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#define DCTLINFO_V2_W4_SEC_ENT4_KEYID GENMASK(27, 26)
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#define DCTLINFO_V2_W4_SEC_ENT5_KEYID GENMASK(29, 28)
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#define DCTLINFO_V2_W4_SEC_ENT6_KEYID GENMASK(31, 30)
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#define DCTLINFO_V2_W4_ALL GENMASK(31, 5)
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#define DCTLINFO_V2_W5_SEC_ENT7_KEYID GENMASK(1, 0)
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#define DCTLINFO_V2_W5_SEC_ENT8_KEYID GENMASK(3, 2)
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#define DCTLINFO_V2_W5_SEC_ENT_VALID_V1 GENMASK(23, 8)
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#define DCTLINFO_V2_W5_SEC_ENT0_V1 GENMASK(31, 24)
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#define DCTLINFO_V2_W5_ALL (GENMASK(31, 8) | GENMASK(3, 0))
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#define DCTLINFO_V2_W6_SEC_ENT1_V1 GENMASK(7, 0)
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#define DCTLINFO_V2_W6_SEC_ENT2_V1 GENMASK(15, 8)
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#define DCTLINFO_V2_W6_SEC_ENT3_V1 GENMASK(23, 16)
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#define DCTLINFO_V2_W6_SEC_ENT4_V1 GENMASK(31, 24)
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#define DCTLINFO_V2_W6_ALL GENMASK(31, 0)
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#define DCTLINFO_V2_W7_SEC_ENT5_V1 GENMASK(7, 0)
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#define DCTLINFO_V2_W7_SEC_ENT6_V1 GENMASK(15, 8)
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#define DCTLINFO_V2_W7_SEC_ENT7 GENMASK(23, 16)
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#define DCTLINFO_V2_W7_SEC_ENT8 GENMASK(31, 24)
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#define DCTLINFO_V2_W7_ALL GENMASK(31, 0)
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#define DCTLINFO_V2_W8_MLD_SMA_L_V1 GENMASK(31, 0)
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#define DCTLINFO_V2_W8_ALL GENMASK(31, 0)
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#define DCTLINFO_V2_W9_MLD_SMA_H_V1 GENMASK(15, 0)
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#define DCTLINFO_V2_W9_MLD_TMA_L_V1 GENMASK(31, 16)
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#define DCTLINFO_V2_W9_ALL GENMASK(31, 0)
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#define DCTLINFO_V2_W10_MLD_TMA_H_V1 GENMASK(31, 0)
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#define DCTLINFO_V2_W10_ALL GENMASK(31, 0)
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#define DCTLINFO_V2_W11_MLD_TA_BSSID_L_V1 GENMASK(31, 0)
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#define DCTLINFO_V2_W11_ALL GENMASK(31, 0)
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#define DCTLINFO_V2_W12_MLD_TA_BSSID_H_V1 GENMASK(15, 0)
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#define DCTLINFO_V2_W12_ALL GENMASK(15, 0)
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int rtw89_cam_init(struct rtw89_dev *rtwdev, struct rtw89_vif *vif);
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void rtw89_cam_deinit(struct rtw89_dev *rtwdev, struct rtw89_vif *vif);
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@@ -3349,6 +3349,10 @@ int rtw89_core_sta_add(struct rtw89_dev *rtwdev,
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if (ret)
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return ret;
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ret = rtw89_chip_h2c_default_dmac_tbl(rtwdev, rtwvif, rtwsta);
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if (ret)
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return ret;
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rtw89_queue_chanctx_change(rtwdev, RTW89_CHANCTX_REMOTE_STA_CHANGE);
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}
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@@ -3207,6 +3207,9 @@ struct rtw89_chip_ops {
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int (*h2c_ampdu_cmac_tbl)(struct rtw89_dev *rtwdev,
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struct ieee80211_vif *vif,
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struct ieee80211_sta *sta);
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int (*h2c_default_dmac_tbl)(struct rtw89_dev *rtwdev,
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struct rtw89_vif *rtwvif,
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struct rtw89_sta *rtwsta);
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int (*h2c_update_beacon)(struct rtw89_dev *rtwdev,
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struct rtw89_vif *rtwvif);
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int (*h2c_ba_cam)(struct rtw89_dev *rtwdev, struct rtw89_sta *rtwsta,
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@@ -1525,6 +1525,61 @@ int rtw89_fw_h2c_dctl_sec_cam_v2(struct rtw89_dev *rtwdev,
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}
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EXPORT_SYMBOL(rtw89_fw_h2c_dctl_sec_cam_v2);
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int rtw89_fw_h2c_default_dmac_tbl_v2(struct rtw89_dev *rtwdev,
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struct rtw89_vif *rtwvif,
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struct rtw89_sta *rtwsta)
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{
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u8 mac_id = rtwsta ? rtwsta->mac_id : rtwvif->mac_id;
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struct rtw89_h2c_dctlinfo_ud_v2 *h2c;
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u32 len = sizeof(*h2c);
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struct sk_buff *skb;
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int ret;
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skb = rtw89_fw_h2c_alloc_skb_with_hdr(rtwdev, len);
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if (!skb) {
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rtw89_err(rtwdev, "failed to alloc skb for dctl v2\n");
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return -ENOMEM;
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}
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skb_put(skb, len);
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h2c = (struct rtw89_h2c_dctlinfo_ud_v2 *)skb->data;
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h2c->c0 = le32_encode_bits(mac_id, DCTLINFO_V2_C0_MACID) |
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le32_encode_bits(1, DCTLINFO_V2_C0_OP);
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h2c->m0 = cpu_to_le32(DCTLINFO_V2_W0_ALL);
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h2c->m1 = cpu_to_le32(DCTLINFO_V2_W1_ALL);
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h2c->m2 = cpu_to_le32(DCTLINFO_V2_W2_ALL);
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h2c->m3 = cpu_to_le32(DCTLINFO_V2_W3_ALL);
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h2c->m4 = cpu_to_le32(DCTLINFO_V2_W4_ALL);
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h2c->m5 = cpu_to_le32(DCTLINFO_V2_W5_ALL);
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h2c->m6 = cpu_to_le32(DCTLINFO_V2_W6_ALL);
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h2c->m7 = cpu_to_le32(DCTLINFO_V2_W7_ALL);
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h2c->m8 = cpu_to_le32(DCTLINFO_V2_W8_ALL);
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h2c->m9 = cpu_to_le32(DCTLINFO_V2_W9_ALL);
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h2c->m10 = cpu_to_le32(DCTLINFO_V2_W10_ALL);
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h2c->m11 = cpu_to_le32(DCTLINFO_V2_W11_ALL);
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h2c->m12 = cpu_to_le32(DCTLINFO_V2_W12_ALL);
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rtw89_h2c_pkt_set_hdr(rtwdev, skb, FWCMD_TYPE_H2C,
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H2C_CAT_MAC,
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H2C_CL_MAC_FR_EXCHG,
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H2C_FUNC_MAC_DCTLINFO_UD_V2, 0, 0,
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len);
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ret = rtw89_h2c_tx(rtwdev, skb, false);
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if (ret) {
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rtw89_err(rtwdev, "failed to send h2c\n");
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goto fail;
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}
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return 0;
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fail:
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dev_kfree_skb_any(skb);
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return ret;
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}
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EXPORT_SYMBOL(rtw89_fw_h2c_default_dmac_tbl_v2);
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int rtw89_fw_h2c_ba_cam(struct rtw89_dev *rtwdev, struct rtw89_sta *rtwsta,
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bool valid, struct ieee80211_ampdu_params *params)
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{
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@@ -3955,6 +3955,9 @@ int rtw89_fw_h2c_default_cmac_tbl(struct rtw89_dev *rtwdev,
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int rtw89_fw_h2c_default_cmac_tbl_g7(struct rtw89_dev *rtwdev,
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struct rtw89_vif *rtwvif,
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struct rtw89_sta *rtwsta);
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int rtw89_fw_h2c_default_dmac_tbl_v2(struct rtw89_dev *rtwdev,
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struct rtw89_vif *rtwvif,
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struct rtw89_sta *rtwsta);
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int rtw89_fw_h2c_assoc_cmac_tbl(struct rtw89_dev *rtwdev,
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struct ieee80211_vif *vif,
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struct ieee80211_sta *sta);
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@@ -4113,6 +4116,18 @@ static inline int rtw89_chip_h2c_default_cmac_tbl(struct rtw89_dev *rtwdev,
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return chip->ops->h2c_default_cmac_tbl(rtwdev, rtwvif, rtwsta);
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}
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static inline int rtw89_chip_h2c_default_dmac_tbl(struct rtw89_dev *rtwdev,
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struct rtw89_vif *rtwvif,
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struct rtw89_sta *rtwsta)
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{
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const struct rtw89_chip_info *chip = rtwdev->chip;
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if (chip->ops->h2c_default_dmac_tbl)
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return chip->ops->h2c_default_dmac_tbl(rtwdev, rtwvif, rtwsta);
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return 0;
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}
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static inline int rtw89_chip_h2c_update_beacon(struct rtw89_dev *rtwdev,
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struct rtw89_vif *rtwvif)
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{
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@@ -4501,6 +4501,10 @@ int rtw89_mac_vif_init(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif)
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if (ret)
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return ret;
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ret = rtw89_chip_h2c_default_dmac_tbl(rtwdev, rtwvif, NULL);
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if (ret)
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return ret;
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return 0;
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}
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@@ -2337,6 +2337,7 @@ static const struct rtw89_chip_ops rtw8851b_chip_ops = {
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.h2c_default_cmac_tbl = rtw89_fw_h2c_default_cmac_tbl,
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.h2c_assoc_cmac_tbl = rtw89_fw_h2c_assoc_cmac_tbl,
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.h2c_ampdu_cmac_tbl = NULL,
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.h2c_default_dmac_tbl = NULL,
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.h2c_update_beacon = rtw89_fw_h2c_update_beacon,
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.h2c_ba_cam = rtw89_fw_h2c_ba_cam,
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@@ -2081,6 +2081,7 @@ static const struct rtw89_chip_ops rtw8852a_chip_ops = {
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.h2c_default_cmac_tbl = rtw89_fw_h2c_default_cmac_tbl,
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.h2c_assoc_cmac_tbl = rtw89_fw_h2c_assoc_cmac_tbl,
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.h2c_ampdu_cmac_tbl = NULL,
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.h2c_default_dmac_tbl = NULL,
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.h2c_update_beacon = rtw89_fw_h2c_update_beacon,
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.h2c_ba_cam = rtw89_fw_h2c_ba_cam,
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@@ -2506,6 +2506,7 @@ static const struct rtw89_chip_ops rtw8852b_chip_ops = {
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.h2c_default_cmac_tbl = rtw89_fw_h2c_default_cmac_tbl,
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.h2c_assoc_cmac_tbl = rtw89_fw_h2c_assoc_cmac_tbl,
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.h2c_ampdu_cmac_tbl = NULL,
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.h2c_default_dmac_tbl = NULL,
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.h2c_update_beacon = rtw89_fw_h2c_update_beacon,
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.h2c_ba_cam = rtw89_fw_h2c_ba_cam,
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@@ -2851,6 +2851,7 @@ static const struct rtw89_chip_ops rtw8852c_chip_ops = {
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.h2c_default_cmac_tbl = rtw89_fw_h2c_default_cmac_tbl,
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.h2c_assoc_cmac_tbl = rtw89_fw_h2c_assoc_cmac_tbl,
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.h2c_ampdu_cmac_tbl = NULL,
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.h2c_default_dmac_tbl = NULL,
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.h2c_update_beacon = rtw89_fw_h2c_update_beacon,
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.h2c_ba_cam = rtw89_fw_h2c_ba_cam,
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@@ -826,6 +826,7 @@ static const struct rtw89_chip_ops rtw8922a_chip_ops = {
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.h2c_default_cmac_tbl = rtw89_fw_h2c_default_cmac_tbl_g7,
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.h2c_assoc_cmac_tbl = rtw89_fw_h2c_assoc_cmac_tbl_g7,
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.h2c_ampdu_cmac_tbl = rtw89_fw_h2c_ampdu_cmac_tbl_g7,
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.h2c_default_dmac_tbl = rtw89_fw_h2c_default_dmac_tbl_v2,
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.h2c_update_beacon = rtw89_fw_h2c_update_beacon_be,
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.h2c_ba_cam = rtw89_fw_h2c_ba_cam_v1,
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};
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