Files
linux/drivers
loanchen f88192d233 drm/amd/display: Correct register address in dcn35
[Why]
the offset address of mmCLK5_spll_field_8 was incorrect for dcn35
which causes SSC not to be enabled.

Reviewed-by: Charlene Liu <charlene.liu@amd.com>
Signed-off-by: Lo-An Chen <lo-an.chen@amd.com>
Signed-off-by: Zaeem Mohamed <zaeem.mohamed@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org
2025-01-28 16:23:30 -05:00
..
2025-01-10 14:24:17 +10:00
2024-11-05 05:33:46 +01:00
2024-11-09 09:14:12 -08:00
2024-11-15 00:32:29 +11:00
2024-11-12 15:48:08 +01:00