linux

mirror of https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git synced 2026-02-19 06:38:26 -05:00

Files

Charlene Liu f1fd8a9ac2 drm/amd/display: Correct sw cache timing to ensure dispclk ramping

[why]
Current driver will cache the dispclk right after send cmd to pmfw,
but actual clock not reached yet.

Change to only cache the dispclk setting after HW reached to the real clock.
Also give some range as it might be in bypass clock setting.

Reviewed-by: Yihan Zhu <yihan.zhu@amd.com>
Signed-off-by: Charlene Liu <Charlene.Liu@amd.com>
Signed-off-by: Ivan Lipski <ivan.lipski@amd.com>
Tested-by: Dan Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

2025-09-23 10:32:20 -04:00

drm

drm/amd/display: Correct sw cache timing to ensure dispclk ramping

2025-09-23 10:32:20 -04:00

host1x

gpu: host1x: Use for_each_available_child_of_node_scoped()

2025-05-07 18:09:30 +02:00

ipu-v3

gpu: ipu-v3: Switch to irq_find_mapping()

2025-05-16 21:06:12 +02:00

nova-core

Merge tag 'drm-rust-next-2025-09-16' of https://gitlab.freedesktop.org/drm/rust/kernel into drm-next